Virtualization as a New Scaling Law for Semiconductor Devices Beyond Geometric Scaling
Zeheng Wang, Xinghuan Chen, Fanfan Lin, Xinze Li, Fangzhou Wang, Songnan Guo, Simin Yu, Liang Li, Jing‐Kai Huang

TL;DR
This paper proposes virtualization as a new way to scale semiconductor devices using AI, reducing reliance on physical testing and fabrication.
Contribution
The paper introduces virtualization as a novel scaling law for semiconductors enabled by AI and virtual evidence.
Findings
AI enables virtualization in design, fabrication, and qualification of semiconductor devices.
Virtual evidence can replace physical iteration, improving efficiency and reducing costs.
Future progress depends on the quality and integration of virtual evidence rather than just geometric scaling.
Abstract
As Moore's‐law–driven geometric scaling nears physical, economic, and sustainability limits, semiconductor progress is increasingly constrained by the cost and latency of physical iteration. This Perspective argues that AI enables virtualization as a complementary scaling law: progress scales with how much trustworthy virtual evidence can replace exhaustive fabrication, testing, and qualification across the device lifecycle. We show how virtualization emerges in i) design and modeling via surrogate and physics‐informed learning, inverse design, and uncertainty‐aware exploration; ii) fabrication and packaging via digital twins, virtual metrology, and reinforcement learning; and iii) qualification via defect inference and reliability modeling that provide earlier risk signals. We outline boundary conditions—trust and uncertainty, cross‐stage coherence, sustainability, and governance—and…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Machine Learning in Materials Science · Big Data and Digital Economy
