Heterosynaptic Memtransistors Based on Switching Operation Mechanism Using Designed Organic/Inorganic Heterostructures for Neuromorphic Electronics

TL;DR

This paper introduces a new type of memtransistor using organic and inorganic materials to mimic brain-like computing functions efficiently.

Contribution

The study introduces a novel gate-pulse-tunable memtransistor design using TCTA/MoS2 heterostructures for neuromorphic electronics.

Findings

Memtransistors with TCTA/MoS2 heterostructures show a switching ratio of 102 modulated by gate pulses.

Non-volatile heterosynaptic behavior is achieved with time constants of 100 ms for potentiation and 60 ms for depression.

The design enables reliable emulation of synaptic plasticity and neuromorphic functions.

Abstract

Memtransistors using low‐dimensional semiconductors represent a promising gate‐tunable heterosynaptic architecture for neuromorphic computing. However, active layers of these devices have not yet been artificially designed or controlled. In this study, gate‐pulse‐tunable heterosynaptic neuromodulation is achieved using memtransistors with organic semiconductor tris(4‐carbazoyl‐9‐ylphenyl)amine (TCTA)/MoS2 heterostructures designed via energy‐band engineering and bottom‐contact architecture. Memristive switching is realized through distinctive low‐ and high‐conduction states with a switching ratio of 102, modulated by gate pulses. As the gate voltage (V
G) decreases from +30 to −30 V, the memristive hysteresis for the bottom contact TCTA/MoS2 FET without post‐treatment and an h‐BN insulating layer appears at V
G = −15 V and broadens with an increasing switching ratio. Intriguingly, as V
G becomes increasingly negative (V
G < −15 V), trap‐related space‐charge‐limited conduction becomes dominant. Non‐volatile heterosynaptic behavior is mimicked by drain pulses and modulated by gate‐pulse polarities. Applying gate‐pulse only, analogous responses are observed in synaptic modulation with time constants of 100 ms for potentiation and 60 ms for depression. The design of multi‐functional memory and realization of gate‐pulse‐tunable memtransistors using nanoscale TCTA/MoS2 can promote energy‐efficient, tunable, and reliable heterosynaptic neuromorphic electronics.

Heteroysynaptic memtransistors are fabricated using a combination of π‐conjugated organic semiconductor TCTA and TMDC MoS2 heterostructure with bottom‐contact architecture. Non‐volatile heterosynaptic and homosynaptic functions such as long‐term plasticity and spike‐timing‐dependent plasticity are emulated by drain and gate pulses based on conduction mechanism switching. Elaborately designed framework can offer reliability and reproducibility for artificial neuromorphic computing systems.

Figures

Bottom‐contact (BC) TCTA/MoS2 memtransistors. (a) Schematic of the BC TCTA/MoS2 memtransistor (top) and corresponding biological neural system (bottom). (b) Energy band alignment of the BC TCTA/MoS2 memtransistor. The TCTA energy band is shown inside the MoS2 layer to reflect the bottom‐contact structure of the TCTA/MoS2 memtransistor. (c) Optical microscopy image of the TCTA/MoS2 memtransistor. The white dotted lines represent sample boundaries. (d) I D–V G transfer characteristic curves of the FETs, measured at V D = 1 V for pristine MoS2 (open black markers) and TCTA/MoS2 (solid red markers). (e) I D–V D output characteristic curves of the pristine MoS2 (open black markers) and TCTA/MoS2 (solid red markers) FETs measured at V G = −20 V.

Gate tunability and charge transport mechanism of memristive switching characteristics. (a) I D–V D output characteristic curves of BC TCTA/MoS2 memtransistors, measured at V G = −30, −15, 0, 15, and 30 V. (b) Dual‐logarithmic plot of the I D–V D curve at V G = −30 V. Schematic energy‐band diagrams showing charge transport at V G < V th with (c) low and (d) high source‐drain bias (V D). Black, orange, and blue arrows represent charge transport, Shockley–Read–Hall, and Langevin recombination, respectively.

Gate‐tunable charge transport mechanism. (a) I D–V D output characteristic curves of TCTA/MoS2 memtransistors at V G = −15 V and (b) corresponding schematic of charge transport at V G ≈ V th. (c) I D–V D output characteristic curves of TCTA/MoS2 memtransistors at V G = 30 V and (d) corresponding schematic of charge transport at V G > V th.

Heterosynaptic and modulatory‐induced homosynaptic characteristics of the TCTA/MoS2 memtransistors. (a) Heterosynaptic long‐term plasticity (H‐LTP) as a function of pre‐impulse (V pre) number with various modulatory impulses (V mod): −40 V (open red markers), 0 V (open black markers), and 30 V (open blue markers). (b) Heterosynaptic spike‐timing‐dependent plasticity (H‐STDP) as a function of the time interval (Δt) between paired V pre under different V mod: −40 V (open red markers), 0 V (open black markers), and 30 V (open blue markers). (c) Modulatory‐induced homosynaptic LTP (M‐LTP) as a function of pulse number under V mod (over 100 pulses). (d) Modulatory‐induced homosynaptic STDP (M‐STDP) as a function of Δt between paired V mod. H‐LTP and H‐STDP were measured using synchronous V pre and V mod, whereas M‐LTP and M‐STDP were measured without V pre.

Tables

TABLE 1. Comparison of key parameters of the BC TCTA/MoS2 memtransistor with other reported memtransistors and memristors.

Device	Active layer	Switching ratio	Operating voltage	Potentiation/Depression time	Refs.
Memtransistor	TCTA/MoS2 HS	∼102	V G = −40–30 V V D = −6–6 V	100 ms/60 ms	This work
	Polycrystalline MoS2	∼102	V G = −50–50 V V D = −80–80 V	2 ms/6 ms	[1]
	MAPbI3‐xBrx/IDT‐BT	∼102	V G = −80–0 V V D = −80–80 V	LTP/LTD observed	[53]
	Rubrene/CulnP2S	—	V G = −60–60 V V D = −80–0 V	—	[54]
	PTCDA/MoS2	—	V G = −20 to −12 V V D = 0.1–1 V	STP/LTP observed	[59]
	DNTT/MoS2		V D = 0.001–0.2 V (No gate voltage used)	STP/LTP Observed	[60]
Synaptic transistor	Organic semiconductor / CuInSe2 QDs	—	V G = −40–10 V V D = −30–0 V	LTP/LTD, STDP observed	[55]
Memristor	MoS2	4–6	0–60 V	—	[37]
	MoS2	∼103	−5–5 V	LTP/LTD observed	[56]
	Al‐HQ hybrid/Al2O3	∼103	V set = 1 V V reset = −0.7 V	2 ms/6 ms	[57]
	ZnO nanorods/PMMA	—	V set = 3 V V reset = −3 V	LTP/LTD observed	[58]

Full text

Introduction

1

Memtransistors based on a carefully selected semiconductor combination and three‐terminal architecture (source, drain, and gate electrodes) can enable energy‐efficient neuromorphic computing via heterosynaptic plastic neural networks [1, 2, 3, 4]. Vertical‐type memristors with top and bottom electrodes have been intensively studied for their dual functions as memory and resistors in non‐volatile resistive random‐access memory and neuromorphic computing applications [5, 6, 7, 8, 9, 10]. These devices can control resistance states by memorizing previous electrical inputs, thereby mimicking the synaptic functions in biological neural networks [11, 12, 13, 14, 15, 16].

Memory‐based neuromorphic devices represent a fundamental advancement toward hardware implementation capable of spiking‐neuron operations. Moving beyond their function as simple memory elements, these devices are uniquely designed to emulate biological synapses, facilitating both synaptic weight storage and neuron firing functionalities that effectively mimic the behavior of the human brain. These neuromorphic architectures offer significant advantages over conventional CMOS‐based neural networks, such as enhanced energy efficiency and the ability to realize highly integrated spiking neural networks (SNNs). Furthermore, their operational performance can be critically optimized through various in situ learning algorithms [15, 17, 18, 19]. Memory‐type neuromorphic devices also provide the foundation for advanced sensory‐perceptive interactive systems. They can directly convert external sensory stimuli into electrical spikes, thereby achieving a unified hardware platform that integrates sensing, signal processing, and decision‐making [15].

Early research on memristive switching focused on metal/transition metal oxide (TMO; e.g., TiO_x_, TaO_x_, AlO_x_, CuO_x_)/metal vertical structures, examining the atomic‐scale movement of metallic ions and vacancies [20, 21, 22, 23]. Accurate atomic‐level control of charge carriers in the metal/TMO/metal configuration enabled various synaptic functions [24, 25]. However, these TMO‐based frameworks should be improved for multi‐functionality tuning of the channel conductance via gate bias and/or pulse for advanced artificial synapses of neuromorphic electronics. To overcome these limitations, 2D transition metal dichalcogenides (TMDCs), such as MoS_2_, WS_2_, WSe_2_, and MoTe_2_, along with graphene, MXene, and h‐BN, have been explored for the development of atomically scaled memristors with vertical structures [26, 27, 28, 29]. In these 2D‐TMDC‐based memristors, featuring vertical and heterojunction (HJ) structures with top and bottom electrodes, memristor switching and synaptic functions were analyzed considering mechanisms such as vacancy migration [30, 31, 32], filament formation [33, 34], phase transition [35, 36], and Schottky to direct tunneling charge transport [37]. Owing to their scalable atomic thickness, these memristors exhibited outstanding energy efficiency with low turn‐on voltages [38, 39]. However, the precise control of charge carriers, ions, defects, trap states, and vacancies remains crucial for achieving the desired performance in neuromorphic electronics. Moreover, the simple two‐terminal structures of memristors using 2D TMDCs as active layers cannot effectively achieve hetero‐integration and multi‐functionality, which are essential for future neuromorphic synaptic elements.

Memtransistors with lateral structures, such as field‐effect transistor (FET) configurations, have been fabricated using monolayer MoS_2_ grown by chemical vapor deposition (CVD) [1, 40]. In such devices, memristor characteristics have been associated with defect migration at grain boundaries in MoS_2_. Although these memtransistors benefited from atomic thickness and multi‐tunable electric signals, precise control of defects and irregular grain boundaries associated with the polycrystalline nature of CVD‐grown monolayer MoS_2_ remained unresolved. Huh et al. reported gate‐pulse‐tunable artificial heterosynaptic architectures using MoS_2_‐channel memtransistors with oxidation‐induced defects [3]. Memristive switching between source and drain was achieved by defect‐mediated space‐charge‐limited conduction (SCLC), modulated by gate voltages. Synaptic weights in three‐terminal MoS_2_ memtransistors were programmed with sub‐femtojoule drain and gate pulses. However, the memristor characteristics, including synaptic functions, strongly depended on the generation of oxidation defects on thin surfaces of MoS_2_ via UV‐ozone treatment. This necessitated precise and reproducible control of defect/trap states and spike‐timing‐dependent plasticity (STDP) learning.

Despite the considerable advances in memristors in recent years, improvements in power consumption, tunability, multi‐functionality, and reliability are required for future neuromorphic electronics. To implement artificial heterosynaptic multi‐functionality, the active layers of memtransistors must be sensibly designed using distinct low‐dimensional heterostructures (HSs) based on energy‐band engineering. Accurate modulation between the high‐resistance state (HRS) and low‐resistance state (LRS), plasticity, and depression can be realized through gate pulses in FETs using such HS‐based active layers. These abilities can enable artificial and precise control of charge currents corresponding to neuron signals. Specifically, heterosynaptic neuromodulation and neurotransmission between pre‐neurons and post‐neurons can facilitate the realization of neuromorphic electronics.

In this study, we fabricated three‐terminal memtransistors with a vertically stacked HS as an active layer consisting of an organic semiconductor tris(4‐carbazoyl‐9‐ylphenyl)amine (TCTA) donor and MoS_2_ acceptor. The TCTA/MoS_2_ HS demonstrated type‐II energy‐band alignment (EBA) and induced low and high current channels for the HRS and LRS. The Fermi‐energy level (E F) in the active layer of the FET could be tuned by gate bias, resulting in multi‐functionality for neuromorphic electronics. By combining a few‐layer MoS_2_ with an ordered nanometer‐thick TCTA layer, artificial synaptic devices with reproducibility could be developed. The bottom‐contact (BC) FETs incorporating the TCTA/MoS_2_ HS exhibited the distinct current channels via gate modulation, realizing the memtransistor with multi‐level configurations. Notably, non‐volatile synaptic behavior was successfully mimicked by drain pulses and modulated by the polarity of the gate pulses. Analogous responses were observed even without drain pulses (i.e., gate‐pulse only condition). To the best of our knowledge, such material selection, gate‐switchable conduction mechanisms, and multi‐input‐based operations within a single FET device using a p‐type‐organic/n‐type‐inorganic TCTA/MoS_2_ HS have not been reported in the literature. The proposed framework provides a promising platform for the design of artificial multi‐functional systems for neuromorphic computing.

Results and Discussion

2

Energy Band and Device Structures

2.1

Figure 1a schematically illustrates the memtransistor (top) and corresponding heterosynaptic neural system (bottom). Based on the concept of the memtransistor, the drain electrode in the FET device corresponds to the pre‐neuron, the source electrode to the post‐neuron, and the gate electrode to the modulatory neuron. Pre‐ and modulatory impulses were simulated by applying voltage pulses to the drain and gate electrodes, respectively. The active layer of the memtransistor was composed of an HS formed by the organic π‐conjugated donor TCTA and inorganic 2D acceptor MoS_2_. As shown in Figure 1b, the TCTA/MoS_2_ HS exhibited a type‐II EBA. The highest occupied molecular orbital and lowest unoccupied molecular orbital levels of TCTA were estimated via ultraviolet photoelectron spectroscopy (UPS) and absorption spectroscopy (Figure S1). The valence band maximum (VBM) and conduction band minimum (CBM) of MoS_2_ were referenced from the literature [41]. Owing to the energy offset between the TCTA and MoS_2_ layers, electrons and holes could be easily transferred through the heterointerface. For the characteristics of the interface and of materials, X‐ray photoelectron spectra (XPS) data of pristine MoS_2_ and TCTA/MoS_2_ heterostructure, absorption and PL spectra of TCTA, AFM images with thickness analysis of MoS_2_ are shown in Figures S2–S4 and Table S1.

Bottom‐contact (BC) TCTA/MoS2 memtransistors. (a) Schematic of the BC TCTA/MoS2 memtransistor (top) and corresponding biological neural system (bottom). (b) Energy band alignment of the BC TCTA/MoS2 memtransistor. The TCTA energy band is shown inside the MoS2 layer to reflect the bottom‐contact structure of the TCTA/MoS2 memtransistor. (c) Optical microscopy image of the TCTA/MoS2 memtransistor. The white dotted lines represent sample boundaries. (d) I D–V G transfer characteristic curves of the FETs, measured at V D = 1 V for pristine MoS2 (open black markers) and TCTA/MoS2 (solid red markers). (e) I D–V D output characteristic curves of the pristine MoS2 (open black markers) and TCTA/MoS2 (solid red markers) FETs measured at V G = −20 V.

Figure 1c shows an optical microscopy image of the device. The channel length and width of the BC TCTA/MoS_2_ FET were 1.32 and 7.51 µm, respectively. Figure 1d shows the transfer characteristic curves (I D–V G) of the BC MoS_2_ FETs at V D = 1 V before (open black markers) and after (solid red markers) hybridization with TCTA. The pristine BC MoS_2_ FET exhibited a high n‐type current with a threshold voltage (V th) near 0 V. In contrast, for the BC TCTA/MoS_2_ FET, V th shifted to −50 V in the forward sweep (red arrow) and −15 V in the backward sweep (blue arrow), accompanied by a wide current saturation region and broad and hard hysteresis within the sweep cycle, as shown in Figure 1d. To comprehensively assess the charge transport mechanism, output characteristic curves (I D–V D) of the pristine BC MoS_2_ (open black markers) and BC TCTA/MoS_2_ (solid red markers) FETs were measured at V G = −20 V (within the hysteresis range of −50 to −15 V) using a cyclic forward and reverse V D sweep from 0 to 3 V (Figure 1e). The BC TCTA/MoS_2_ FET exhibited a distinct hysteresis loop with clear resistance switching, while the pristine BC MoS_2_ FET showed typical n‐type diode‐like behavior. Notably, such large hysteresis was not observed in the top‐contact (TC) FETs (Figure S5). In the BC FETs, the source–drain (S–D) electrodes contacted only the MoS_2_ layer, whereas in the TC FETs, the S‐D electrodes contacted both MoS_2_ and TCTA (Figures S5 and S6). Using a higher V D = 2 V, transfer characteristic curves (I D–V G) similar to those in Figure 1d were observed (Figure S7a). The hysteretic output characteristic curves (I D–V D) were observed for the BC TCTA/MoS_2_ FET with negative gate voltages (−20 and −30 V), as shown in Figure S7b–h. The observed memristive switching behavior and gate‐tunable three‐terminal architecture of the BC TCTA/MoS_2_ FET could facilitate multi‐level configurations for heterosynaptic systems such as memtransistors.

Memtransistor Characteristics

2.2

To explore gate tunability, the output characteristic curves (I D–V D) of the BC TCTA/MoS_2_ memtransistor were measured at various V G (−30, −20, −15, −10, 0, 10, 15, 20, and 30 V), as shown in Figure 2a and Figure S7. As V G negatively increased from +30 to −30 V, memristive hysteresis broadened with increasing the switching ratio up to 10^2^. It should be noted that no post‐treatment was performed to induce extrinsic traps in the MoS_2_ and TCTA layers, and no h‐BN insulating layer was adopted. These imply that the switching characteristics of our memtransistor are attributed to the hybridization with organic TCTA in the BC FET structure. Memristive switching was clearly observed in the BC TCTA/MoS_2_ FETs after the formation of the HS (Figure 2a). The memristive hysteresis characteristics were only observed for the BC TCTA/MoS_2_ FETs at high negative V G, not for the TC TCTA/MoS_2_ FETs (Figure S8).

Gate tunability and charge transport mechanism of memristive switching characteristics. (a) I D–V D output characteristic curves of BC TCTA/MoS2 memtransistors, measured at V G = −30, −15, 0, 15, and 30 V. (b) Dual‐logarithmic plot of the I D–V D curve at V G = −30 V. Schematic energy‐band diagrams showing charge transport at V G < V th with (c) low and (d) high source‐drain bias (V D). Black, orange, and blue arrows represent charge transport, Shockley–Read–Hall, and Langevin recombination, respectively.

The output characteristics of the BC TCTA/MoS_2_ memtransistor were analyzed through the power‐law relation (I D ∝ V D ^m^) based on the SCLC model [3, 42], described by the Mott–Gurney law [43, 44]:

$$[eqn]$$

where J, θ, µ, ε 0, ε r, V, and L represent the current density, ratio of free to total carrier concentration, mobility, vacuum permittivity, relative dielectric constant, applied voltage, and channel length, respectively. Assuming the occupation of exponentially distributed traps, J can be described using the trap‐filled‐limited (TFL) SCLC model, described by the Mark–Helfrich law [45]:

$$[eqn]$$

where e, N eff, and N t denote the elementary charge, effective density of states, and total trap density, respectively. The parameter l, which represents the ratio of trap‐related characteristic energy to the measured thermal energy (i.e., l = k B T c/k B T), is typically larger than or equal to 1.

Figure 2b shows the dual‐logarithmic plot of I D–V D in the range of 0.1–3 V at V G = −30 V. Owing to the application of this negative V G, the Fermi level (E F) shifted downward toward the VBM (Figure 2c). Additionally, when V G was lower than V th = −15 V, electrons in MoS_2_ and holes in TCTA accumulated near the HJ interface (Figure S6a). Electrons (holes) could be transferred across the TCTA and MoS_2_ layers at the HJ through the Shockley–Read–Hall (SRH) trap‐intermediated tunneling process and Langevin recombination [46, 47]. In the case of V D ≤ 1 V [Region I (HRS)], I D remained below 10^−11^ A owing to the low charge density. As V D increased further [Region II (SET)], additional charges were injected into the MoS_2_, leading to high charge concentration near the HJ interface (Figure 2d). These accumulated charges led to space‐charge formation, inducing TFL‐dominated charge transport with a slope of m = 5.89 in the plot of I D ∝ V D ^m^. In addition, these charges enhanced the interface recombination rate, resulting in the formation of a p‐type channel in TCTA. Therefore, in the V G < V th condition, owing to the formation of the TCTA channel (SET process), the charges near E F were effectively transported through the n–p–n junction (MoS_2_–TCTA–MoS_2_), contributing to memristive behavior. During backward sweep (from V D = 3 to 0 V), a highly saturated current was observed [0.7 V ≤ V D ≤ 3 V, Region III (LRS)]. Subsequently, I D rapidly decreased with a slope of m = 4.29 in I D ∝ V D ^m^ [0.3 V ≤ V D ≤ 0.7 V, Region IV (RESET)], indicating reduced charge injection and tunneling rate. When V D ≤ 0.3 V [region V (RESET)], trap‐limited SCLC behavior (m = 2.08) was observed owing to the presence of deep‐trapped charges in the TCTA and at the interface channel [3].

To further investigate the gate‐dependent charge transport through the interface, the trap density (N t) was estimated using gate‐dependent output characteristics in Figure S9. As V G varied from −15 to −30 V, V TFL (voltage with filled traps) and N t increased from 0.36 V and 8.95 × 10^13^ cm^−3^ to 1.52 V and 4.14 × 10^14^ cm^−3^, respectively (Table S2). These results indicate that the negative gate bias enhanced both the current level and N t in the active layer of TCTA/MoS_2_, suggesting a gate‐dependent switching mechanism.

The charge transport mechanism of the BC TCTA/MoS_2_ memtransistors was investigated through I D–V D output characteristic curves and energy‐band models at V G = −15 and 30 V, as shown in Figure 3. At V G = −15 V, near the V th (Figure 3a), E F shifted slightly upward (Figure 3b). Charge transport was initially governed by SCLC (m = 2.11), followed by modest TFL conduction (m = 3.87), up to V D = 1.0 V. At V D > 1.0 V, I D exhibited ohmic behavior (m = 1.03), suggestive of the saturation regime in SCLC [48]. Notably, under a low negative V G (= −15 V), the hysteresis of the output I D narrowed (Figure 3a). At V G = 30 V (> V th; Figure 3c), E F shifted upward toward the CBM of MoS_2_ (Figure 3d). In this regime, electrons were tunneled through the metal–semiconductor contact barrier, inducing n‐channel current in the MoS_2_ (Figure S6b). At V G = 30 V, Schottky conduction dominated the charge transport mechanism. As V G became increasingly negative, SCLC emerged as the dominant conduction mechanism, supporting the gate‐dependent charge transport model (Figure S10 and Table S3). At positive V G, I D rapidly increased as V D increased up to 0.7 V owing to the lowering (and/or narrowing) of the Schottky barrier. For V D ≥ 0.7 V, I D became saturated (I sat). Specifically, owing to the high V D, the S–D electric field induced the pinch‐off state in the MoS_2_ channel. The plot of I sat ^1/2^ vs. V G obtained from the I D–V D curves at various positive V G exhibited a linear relationship (Figure S11), consistent with the typical current saturation observed in FETs (I sat ∼ V G ^2^) [48]. Overall, the observed gate‐tunable memristive switching characteristics in BC TCTA/MoS_2_ memtransistors could be explained using the trap‐related SCLC model.

Gate‐tunable charge transport mechanism. (a) I D–V D output characteristic curves of TCTA/MoS2 memtransistors at V G = −15 V and (b) corresponding schematic of charge transport at V G ≈ V th. (c) I D–V D output characteristic curves of TCTA/MoS2 memtransistors at V G = 30 V and (d) corresponding schematic of charge transport at V G > V th.

Control Devices and Neural Functions of Memtransistors

2.3

Analogous to long‐term plasticity (LTP) and STDP in biological synapses, the conductance of FETs can be modulated by consecutive voltage pulses applied to the drain terminal, a phenomenon known as homosynaptic plasticity [49]. Owing to the memristive switching characteristics of our three‐terminal TCTA/MoS_2_ memtransistors, heterosynaptic plasticity could be realized, with gate modulation influencing the underlying charge transport mechanism even without direct stimulation at the drain. The BC TCTA/MoS_2_ memtransistors studied herein mimicked the synaptic functions via tunable and non‐volatile changes in post‐synaptic current (PSC) in response to electrical stimuli. In this model, the drain, source, and gate terminals served as the pre‐neuron, post‐neuron, and modulatory neuron in biological neuron systems, respectively.

Figure 4 shows the heterosynaptic (H‐) and modulatory‐induced homosynaptic (M‐) characteristics along with their measurement conditions (Figure S12). During all measurements, the pulse width (t width) was fixed at 5 ms, and the read voltage pulse (V read) was set as −3 V. As shown in Figure 4a, the H‐LTP process was activated by applying 30 potentiation pulses to the drain (V pre = 6 V), followed by 30 depression pulses (V pre = −6 V). Without gate‐modulation pulses (V mod = 0 V), the PSC increased only slightly during potentiation, whereas it decreased under depression (open black markers in Figure 4a). Interestingly, the PSC depended strongly on the polarity of V mod: the synaptic response was enhanced at V mod = −40 V (open red markers in Figure 4a). In contrast, at V mod = 30 V, the PSC was suppressed (open blue markers in Figure 4a). These polarity‐dependent characteristics are qualitatively consistent with the gate‐dependent output characteristics for the BC TCTA/MoS_2_ memtransistors (Figure 3). Furthermore, the H‐STDP process was investigated using the same values of voltage and pulse widths as those in the LTP process, albeit with a different pulse sequence (Figure 4b). In memristive systems, the synaptic weight w represents the synaptic strength, that is, the strength of connection between pre‐ and post‐neurons in biological systems, and it can be expressed as: [50, 51]

$$[eqn]$$

where I 0 and I STDP denote the measured current before and after applying paired pulses, respectively, imitating the biological activations of pre‐ and post‐neurons [1]. In neural systems, when the post‐neuron is activated after the pre‐neuron, i.e., the time interval (Δt = t post−t pre) of the impulses is positive (Δt > 0), the connection of the two neurons is strengthened. For Δt < 0, the two neurons are not connected, resulting in the weakening of synaptic connections. These processes are key mechanisms in neural systems for energy‐efficient learning and memorizing. In addition, w as a function of Δt is related to the activity‐dependent synaptic behavior, described as an exponential decay function [51, 52],

$$[eqn]$$

where A and τ denote the maximum change and time constant, respectively, and subscripts + and − correspond to positive and negative Δt, respectively. Notably, at V mod = −40 V (red markers in Figure 4b), w exhibited enhanced responses during potentiation (Δt > 0) and weak responses during depression (Δt < 0), compared with those in the case with V mod = 0 V (black markers in Figure 4b). In contrast, at V mod = 30 V (blue markers in Figure 4b), w reduced in the potentiation region (Δt > 0) but was enhanced in the depression regime (Δt < 0). These results clearly demonstrate polarity‐dependent synaptic modulation, in accordance with H‐LTP, suggesting the ability of the BC TCTA/MoS_2_ memtransistors to mimic neuromodulated heterosynaptic plasticity.

Heterosynaptic and modulatory‐induced homosynaptic characteristics of the TCTA/MoS2 memtransistors. (a) Heterosynaptic long‐term plasticity (H‐LTP) as a function of pre‐impulse (V pre) number with various modulatory impulses (V mod): −40 V (open red markers), 0 V (open black markers), and 30 V (open blue markers). (b) Heterosynaptic spike‐timing‐dependent plasticity (H‐STDP) as a function of the time interval (Δt) between paired V pre under different V mod: −40 V (open red markers), 0 V (open black markers), and 30 V (open blue markers). (c) Modulatory‐induced homosynaptic LTP (M‐LTP) as a function of pulse number under V mod (over 100 pulses). (d) Modulatory‐induced homosynaptic STDP (M‐STDP) as a function of Δt between paired V mod. H‐LTP and H‐STDP were measured using synchronous V pre and V mod, whereas M‐LTP and M‐STDP were measured without V pre.

Modulatory‐induced homosynaptic (M‐) plasticity (i.e., in the absence of V pre) was investigated for the same BC TCTA/MoS_2_ memtransistors. As shown in Figure 4c (M‐LTP), the PSC gradually increased during potentiation (V mod = −40 V with 100 pulses) and sequentially decreased during depression (V mod = 30 V with 100 pulses). In addition, the M‐STDP (Figure 4d) demonstrated polarity‐dependent strengthening (with V mod = −40 V) and weakening (with V mod = 30 V). Notably, the w in M‐STDP presented characteristic decay curves with τ + = 100 ms for potentiation (Δt > 0) and τ − = 60 ms for depression (Δt < 0). These results are strongly correlated with the gate controllability in H‐plasticity, supporting the polarity‐dependent memristive synaptic characteristics of the BC TCTA/MoS_2_ memtransistors. The similar gate‐modulated synaptic behaviors were observed in different batches of the BC TCTA/MoS_2_ memtransistors, indicating reproducibility (Figure S13).

Discussion

3

Previous studies on organic/inorganic memristors with vertical or planar structures have focused on hybrid effects and photo‐induced activation, including the incorporation of interface modification and defect engineering to realize neuromorphic computing [53, 54, 55, 56, 57, 58]. Although these devices exhibit resistive‐switching‐based memory characteristics, few studies have quantitatively demonstrated synaptic weight modulation or analyzed STDP behavior. In contrast, three‐terminal memtransistor architectures based on FET configurations have recently garnered attention as a promising route toward heterosynaptic modulation, enabling direct tuning of the channel conductance via gate bias. Wang et al. reported a multi‐functional synaptic transistor based on perylene‐3,4,9,10‐tetracarboxylic dianhydride (PTCDA) / MoS_2_ hybrid heterojunction, with flexible tunability of STP and LTP [59]. Photonic synaptic transistors based on dinaphtho[2,3‐b:2’,3’‐f]thieno[3,2‐b]thiophene (DNTT) / MoS_2_ organic semiconductor heterojunction demonstrated a low energy consumption of 0.4 fJ per synaptic event with ultraweak light intensity of 40 nW cm^−2^ for neuromorphic computing [60]. However, systematic quantification of STDP remains insufficient even in these multi‐terminal structures, which often require intricate fabrication steps, such as the insertion of ferroelectric layers or the induction of photo‐assisted ion migration, to realize synaptic functionality [54, 55].

The BC TCTA/MoS_2_ memtransistors presented in this study address these challenges. Without additional defect‐generation or surface‐modification processes, our BC TCTA/MoS_2_ memtransistors exhibited STDP behavior that could be quantitatively analyzed (τ + = 100 ms, τ − = 60 ms) and reproducible synaptic weight modulation solely under gate‐pulse operation. Moreover, the memtransistors were fabricated with a simple bottom‐contact heterojunction structure composed of a π‐conjugated organic semiconductor (TCTA) and a 2D inorganic semiconductor (MoS_2_), without using h‐BN insulating layers or post‐treatment steps, while maintaining stable electrical characteristics. This reproducible heterojunction configuration demonstrated consistent memristive switching (on/off ≈ 10^2^) and stable heterosynaptic plasticity across different batches of devices. Therefore, the proposed architecture effectively bridges the gap between non‐tunable two‐terminal memristors and complex multi‐terminal synaptic transistors, offering a scalable and reliable platform for next‐generation neuromorphic electronic systems. For future work of our BC TCTA/MoS_2_ memtransistors, to reduce the power consumption and the degradation of dielectric layer over cycles in memtransistors, their working gate voltage should be reduced by optimizing the energy‐band offset of TCTA/MoS_2_ heterojunctions to increase charge transfer efficiency, integrating high‐κ ‐ dielectrics (e.g., HfO_2_, ZrSiO_4_, ZrO_2_, Al_2_O_3_) and/or ferroelectrics to enhance gate electric field coupling, or thinning the active layer to reduce resistance and lower voltage? requirements.

Recent reviews on future neuromorphic applications of memresistive devices provide potential solutions for efficient brain‐inspired computation with memristive implementations: as accelerators for deep learning and artificial intelligence and as building blocks for spiking neural networks and in‐sensor computing [10, 61, 62, 63].

Conclusion

4

Novel memtransistors incorporating TCTA and MoS_2_ HSs as the active layer were designed using type‐II energy‐band engineering and a BC architecture. Memristive switching was achieved via gate‐pulse modulation. Memristor characteristics with SET and RESET hysteresis in the V G < V th regime could be interpreted through the trap‐related SCLC model. The devices successfully mimicked synaptic functions via tunable and non‐volatile changes in PSC in response to electrical stimuli, with the drain, source, and gate terminals functioning as the pre‐neuron, post‐neuron, and modulatory neuron in biological neuron systems, respectively. Measured current vs. voltage transfer and output characteristics at various gate biases/pulses clearly demonstrated polarity‐dependent synaptic behavior, consistent with H‐LTP, highlighting the capability of emulating neuromodulated heterosynaptic plasticity. This work highlights the potential of the designed organic/inorganic‐semiconducting HSs for memtransistors in promoting the implementation of reliable neuromorphic electronics.

Experimental Section

5

Device Fabrication

5.1

TCTA powder (purity > 98.0%) was purchased from Ossila and used without further purification. SiO_2_/Si substrates were sonicated for 5 min in acetone, cleaned with isopropyl alcohol, and treated with ozone for 30 min. The TC and BC FETs were fabricated under identical conditions, except for their stacking sequences. For the TC FETs, few‐layer (∼10 nm) MoS_2_ (HQ Graphene) flakes were mechanically exfoliated and transferred onto the ozone‐treated SiO_2_/Si substrates. Subsequently, Au/Ti (50/5 nm) electrodes were deposited onto the MoS_2_ layer via e‐beam lithography with conventional thermal evaporation. For the BC FETs, the electrodes were patterned first, and the exfoliated MoS_2_ flakes were transferred onto them later. To prepare the p–n HS, TCTA with a thickness of 30 nm was deposited onto the TC and BC pristine MoS_2_ FETs using a custom‐built organic molecular beam deposition equipment (DAEKI High‐Tech.) at a deposition rate of 1 nm min^−1^ under ∼10^−6^ Torr.

Measurements

5.2

Electrical measurements were performed in a vacuum probe station at 295 K under ∼60 mTorr using source‐measure units (237 and 2634B; Keithley). The drain voltage was swept from −3 to 3 V, and the gate voltage was varied from −30 to 30 V. Synaptic behaviors including LTP and STDP were characterized using custom Python programs based on the built‐in commands of the 2634B unit, along with an oscilloscope (TDS 2022C; Tektronix). A read pulse of −3 V was applied to the drain. For pre‐synaptic pulses, +6 and −6 V were applied to the drain. For modulatory pulses, −40, 0, and 30 V were applied to the gate. The pulse width was fixed at 5 ms, and the interval was varied between 5 and 50 ms. Details of the synaptic function measurement conditions and sequences are presented in the SI. UPS was performed using a Nexsa system (Thermo Fisher Scientific) with an excitation source of He I (21.22 eV) at the Korea Institute of Science and Technology. UV–visible (UV–vis) absorbance spectra were measured using a UV/vis spectrometer (8453; Agilent).

Conflicts of Interest

The authors declare no conflicts of interest.

Supporting information

Supporting file: advs73598‐sup‐0001‐SuppMat.docx