A Low-Noise, Low-Power, and Wide-Bandwidth Regulated Cascode Transimpedance Amplifier with Cascode-Feedback in 40 nm CMOS

TL;DR

This paper introduces a new transimpedance amplifier design for optical applications that achieves high bandwidth, low noise, and low power consumption in 40 nm CMOS.

Contribution

A novel regulated cascode TIA with cascode-feedback is proposed, offering improved bandwidth, noise reduction, and power efficiency.

Findings

The proposed TIA achieves a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ.

The design consumes only 6.6 mW at 1.2 V, excluding the output buffer.

It provides a 7.4× to 243× improvement in figure of merit compared to prior RGC TIA designs.

Abstract

The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/Hz. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit.

Figures

Full text

1. Introduction

With the dramatic increase in the emerging optical applications, including Lidar, short-range optical communication, optical wireless communication, as well as optical integrated sensing and communication (ISAC) [1,2,3,4,5,6], the demand for high-speed optical receivers is growing rapidly. In the optical receivers, the analog front-end (AFE) determines the key performance of the whole transmission system, such as bandwidth and noise [7,8]. Figure 1 shows the front-end of an optical receiver, consisting of a photodiode (PD), a transimpedance amplifier (TIA), a limiting amplifier (LA), and an output buffer (OB) [9]. As the key optoelectronic interface, the PD transforms the received optical signal into a weak photo-current signal. The TIA then converts the weak photo-current signal to a normal voltage signal with a good signal-to-noise ratio (SNR), which is further amplified by the LA and driven by OB for post-processing. As the first stage of the receiver AFE circuit, the TIA faces a formidable challenge in achieving high bandwidth for high-speed data transmission while ensuring low input-referred noise current for sensitivity and low power consumption to minimize the operating cost of the optical system [10].

Traditionally, the AFE circuits and devices are fabricated by conventional III/V or SiGe technologies for their speed and noise advantages. However, those technologies are no longer suitable for high-integration-density and cost-sensitive applications. Advanced CMOS process has become more popular for its lower cost and higher integration density; however, the lower supply voltage poses a significant challenge to broadband circuit design.

In TIA designs, bandwidth is mainly restricted by the large PD parasitic capacitance $[eqn]$ at the input node [11,12], especially the inverter-based TIA with shunt-shunt feedback in [13,14,15,16]. To realize high-bandwidth TIAs, different topologies for reducing input impedance $[eqn]$ have been adopted. The regulated cascode (RGC) TIA is designed in [17,18] to reduce $[eqn]$ and thus the bandwidth-limiting impact of $[eqn]$ . The dual-feedback modified RGC TIA in [19,20,21] further reduces $[eqn]$ by an additional feedback path. Nevertheless, this comes at the cost of decreased gain due to the output resistance $[eqn]$ reduction. In [22,23], the dual-feedback structure is incorporated with the current-reuse technique to decouple the $[eqn]$ -gain trade-off. However, both modified RGC structures with complex feedback paths severely limit the bandwidth and also inevitably introduce notable noise, which is the first design challenge in high-bandwidth RGC TIA designs.

For low-frequency analog circuit design in conventional CMOS technology, transistor channel lengths are normally sized around or above 1 μm to achieve high output resistance $[eqn]$ . In contrast, for high-frequency wide-bandwidth circuit design in advanced CMOS technology, transistors are sized to the minimal channel length to ensure adequate cut-off frequency $[eqn]$ , whereas $[eqn]$ is significantly degraded. In addition, the RGC topology in [18,23,24] requires large voltage headroom to bias the transistors in strong inversion to achieve high $[eqn]$ , which is not feasible in advanced CMOS processes with low supply voltage near 1 V, limiting the bandwidth performance through three aspects of feedback gain, input resistance, and the Miller effect. Furthermore, the modified RGC TIA designs operating at low voltage in [21,25,26] require large bias current to ensure high $[eqn]$ of the transistors in strong inversion, increasing the overall power consumption. Therefore, the second design challenge lies in the constraint faced by low-power RGC TIAs when implemented in advanced CMOS technology with low supply voltages.

To solve the aforementioned major design challenges, this paper proposes a novel RGC TIA to overcome the bandwidth limitations faced by the existing RGC TIA and at the same time achieve low power and low noise in an advanced CMOS process (the basic TIA circuit was first briefly presented at the ICCS2023 conference [27]). The major contributions of this work are listed as follows:

(1)To address the issues of limited bandwidth and noise in the existing designs such as the dual-feedback RGC TIAs, a single-stage cascode feedback structure is employed as the feedback amplifier in the proposed RGC input stage to boost feedback gain and also reduce Miller capacitance at the input node. By increasing the pole frequency, the bandwidth is dramatically extended for isolating the large $[eqn]$ from bandwidth determination. To balance the bandwidth, gain, and noise, a bandwidth-extension stage with capacitive degeneration and three gain-boosting stages with near-zero noise are cascaded after the RGC input stage with negligible noise contribution to the proposed TIA design.(2)To address the issues of high supply voltage and bias current in the existing RGC TIA works with transistors working in strong inversion for sufficient $[eqn]$ , the design strategy under low supply voltage near 1 V required by advanced process technology below 65 nm is discussed. The design strategy suggests biasing the common-source (CS) feedback transistor in weak inversion to achieve sufficient voltage headroom and improve the power and noise efficiency of the CS transistor with enough $[eqn]$ in advanced CMOS technology. Therefore, the design strategy enables the proposed TIA to achieve considerable bandwidth and much lower power under low supply voltage.(3)To characterize the bandwidth and noise of the proposed RGC TIA, the frequency response and noise analysis are carried out. By the pole-zero analysis based on derived pole-zero equations and precise setting of the pole-zero frequencies, the proposed TIA achieves a flat frequency response within a wide bandwidth. In addition, by the noise analysis based on the derived input-referred noise current of the RGC TIA, the noise-critical devices are identified, and therefore, the dimensions of these key devices are optimized for effective noise reduction.

The paper is organized as follows: In Section 2, the proposed RGC TIA is presented. Section 2.1 and Section 2.2 discuss the modified RGC input stage with the design strategy under low supply voltage, corresponding to contributions (1) and (2), respectively. Section 2.3 introduces the following bandwidth extension and gain-boosting stages. Section 2.4 and Section 2.5 elaborate on the frequency response and noise analysis for contribution (3). Section 3 presents the simulation results and the comparison with the existing 10 Gb/s TIA designs in CMOS technology. Finally, Section 4 draws the conclusions.

2. Modified RGC TIA Design

Figure 2 depicts the schematic of the proposed broadband RGC TIA, consisting of a single-stage cascode-feedback RGC input stage ( $[eqn]$ ), a bandwidth-extension stage with capacitive degeneration ( $[eqn]$ ), three gain-boosting CS stages ( $[eqn]$ ), and a CS output buffer ( $[eqn]$ ) for impedance matching and output measurement. At the input node, a current source $[eqn]$ and a capacitor $[eqn]$ of 0.15 pF [28] are connected in parallel to simulate the output current and junction capacitance of the PD, respectively. A load capacitance $[eqn]$ of 0.15 pF is connected between the TIA output and ground for simulating the pad capacitance and the loading capacitance of subsequent circuits.

2.1. Cascode-Feedback RGC Input Stage

In this section, the single-stage cascode feedback mentioned in contribution 1 is discussed in detail.

Figure 3a shows the conventional RGC structure consisting of the common-gate input transistor $[eqn]$ and the CS feedback amplifier (M_2_ & R_3_), which provides a low input impedance with strong local feedback. The transimpedance gain $[eqn]$ and the input resistance $[eqn]$ are shown as [29]

$$[eqn]$$ $$[eqn]$$

in which A is the gain of the CS amplifier and g_m1_ is the transconductor of M_1_.

The pole frequency located at the input node is determined by the input impedance R_in_ and the lumped capacitance, which is given by

$$[eqn]$$

where $[eqn]$ , $[eqn]$ , $[eqn]$ and $[eqn]$ is the PD capacitance, the Miller capacitance resulted from $[eqn]$ , $[eqn]$ , and $[eqn]$ , respectively. A lower input impedance can help to increase the input node’s pole frequency even with a large $[eqn]$ .

Based on the aforementioned principle analysis of conventional RGC in Figure 3a, the proposed RGC in Figure 3b is specifically designed to utilize the single-stage cascode feedback (M_2_ & M_3_) to provide a higher feedback gain for reducing both input resistance and the Miller effect under low supply voltage through three aspects as below.

Firstly, the gain of the proposed RGC input stage is boosted by the cascode feedback. As depicted in Figure 3a, the attainable gain $[eqn]$ of CS feedback amplifier (M_2_ & R_3_) in the conventional RGC is shown as

$$[eqn]$$ $$[eqn]$$

where $[eqn]$ is the node voltage at the gate of $[eqn]$ and $[eqn]$ is the output resistance of $[eqn]$ . When M_2_ is sized to around minimal channel length to reduce parasitics and power, $[eqn]$ becomes as large as $[eqn]$ , thereby halving the gain as compared to the long channel length case. In order to compensate the gain reduction, the cascaded transistor $[eqn]$ in Figure 3b is employed to increase $[eqn]$ to $[eqn]$ ′, as described by

$$[eqn]$$

Secondly, the input resistance of the proposed RGC input stage is reduced by the cascode feedback. As shown in Figure 3a, the low supply voltage around 1 V forces the CS feedback transistor M_2_ to be sized wider to have a larger bias current for achieving sufficient transconductance $[eqn]$ , leading to a significantly higher power and a larger parasitic capacitance. For low-voltage operation at 1.2 V, the CS transistor $[eqn]$ of the proposed cascode feedback in Figure 3b is biased in the weak inversion region instead so as to achieve sufficient voltage headroom and also exploit a higher transconductance efficiency of $[eqn]$ in the sub-threshold operation of M_2_. Therefore, $[eqn]$ can achieve a large $[eqn]$ with a small bias current $[eqn]$ under a low voltage of 1.2 V, thereby having a large feedback gain to reduce the input resistance R_in_.

Thirdly, the Miller effect of the proposed RGC input stage is reduced by the cascode feedback. As shown in Figure 3a, a wide channel width of M_2_ is to achieve a sufficient g_m2_ and feedback gain, but it introduces a large Miller capacitance at the input node of the conventional RGC, as described by

$$[eqn]$$

where C_M_ is the Miller capacitance and C_gd2_ is the gate-drain capacitance of M_2_. In the proposed cascode feedback in Figure 3b, the Miller effect of $[eqn]$ in weak inversion is reduced by the cascaded transistor $[eqn]$ , as described by

$$[eqn]$$

where $[eqn]$ is comparable to $[eqn]$ . Therefore, $[eqn]$ capacitance is around two times larger than C_gd2_, which is significantly smaller than that without $[eqn]$ , as described by Equation (7).

Based on the above analysis, Table 1 compares the key factors limiting bandwidth of the proposed RGC input stage in Figure 3b and the conventional RGC structure in Figure 3a. By reducing input resistance $[eqn]$ and Miller effect $[eqn]$ under low supply voltage of 1.2 V, the proposed design pushes the input node pole frequency to a higher frequency range, thus achieving a broader bandwidth without introducing a large amount of extra noise or power overhead.

2.2. Design Strategy Under Low Supply Voltage

In the RGC input stage, the gain of feedback loop can be derived as

$$[eqn]$$

which requires a large transconductance efficiency $[eqn]$ of $[eqn]$ and a large voltage drop on $[eqn]$ . The supply voltage of the proposed RGC structure is shown as

$$[eqn]$$

where $[eqn]$ equals to $[eqn]$ , the voltage drop on $[eqn]$ .

The output voltage and swing of the RGC stage are shown as

$$[eqn]$$ $$[eqn]$$

where $[eqn]$ is the voltage drop on $[eqn]$ . Constrained by the saturation-region operation of $[eqn]$ , the output swing can be recalculated by

$$[eqn]$$ $$[eqn]$$ $$[eqn]$$

where $[eqn]$ and $[eqn]$ are the gate voltage and threshold voltage of $[eqn]$ , respectively. By equating (10b) and (11c), the voltage drop on $[eqn]$ is described by

$$[eqn]$$

According to Equations (8) and (9), with the $[eqn]$ plus the low supply voltage requirements, $[eqn]$ is biased in strong inversion to achieve high $[eqn]$ , while $[eqn]$ is biased in weak inversion for better power and noise efficiency, and their $[eqn]$ values can be set accordingly. $[eqn]$ can be calculated from $[eqn]$ method. Therefore, $[eqn]$ ’s voltage drop $[eqn]$ is determined by Equation (9) and then $[eqn]$ is obtained by Equation (8). Having known $[eqn]$ , $[eqn]$ and $[eqn]$ can be set by choosing the wanted value 50 $[eqn]$ of input impedance in Equation (2), then the channel width $[eqn]$ of $[eqn]$ device can be obtained. Since $[eqn]$ is constant, a larger $[eqn]$ with a smaller $[eqn]$ consumes less power. Similarly, with certain $[eqn]$ and $[eqn]$ , the width $[eqn]$ of $[eqn]$ device can also be derived.

In contrast to the conventional RGC structure with both $[eqn]$ and $[eqn]$ working in strong inversion, the proposed RGC structure biases $[eqn]$ in weak inversion, which contributes a lower $[eqn]$ and thus enables a larger $[eqn]$ , as shown in (9). Therefore, a higher feedback gain $[eqn]$ is achieved via (8), and a larger output swing is obtained from (12). In (12), since $[eqn]$ is pre-determined by $[eqn]$ (for $[eqn]$ ’s saturation-region operation) and $[eqn]$ (for 50 $[eqn]$ input impedance), the larger output swing $[eqn]$ enables a larger $[eqn]$ , thereby achieving a higher transimpedance gain of the RGC structure, as depicted in (1).

2.3. Bandwidth Extension and Gain-Boosting Stage

Limited by the large $[eqn]$ , the bandwidth of the single-stage cascode-feedback RGC input stage can hardly be further extended without the degradation of gain and noise performance. Therefore, the capacitive degeneration technique is utilized in the bandwidth extension stage to compensate the dominant pole $[eqn]$ with a zero $[eqn]$ at $[eqn]$ . The detailed pole-zero analysis is presented in the next section, Section 2.3. Therefore, as the dominant pole is compensated by the zero, the −3 dB bandwidth of the TIA is determined by the second lowest pole in the TIA and further extended with minimal noise and area overhead.

Note that $[eqn]$ in the capacitive degeneration trades gain for bandwidth, and therefore, three gain-boosting CS stages are employed to compensate for the gain loss. Moreover, considering the load resistors of the gain-boosting stages degrades the bandwidth performance, $[eqn]$ is set to a lower frequency than $[eqn]$ to realize pre-equalization in the transimpedance response of the proposed TIA.

2.4. Frequency Response

The dc transimpedance gain of the proposed TIA is given by

$$[eqn]$$

In (13), $[eqn]$ is the voltage gain of CS stage formed by $[eqn]$ and $[eqn]$ , where x is from 5 to 8. $[eqn]$ determines the gain of the cascode-feedback RGC input stage according to (1). In this design, the gain of bandwidth-extension stage ( $[eqn]$ ) and the output buffer stage ( $[eqn]$ ) are approximately 1 for pre-equalization and impedance matching, respectively. As a result, the dc gain of the proposed TIA is mainly provided by $[eqn]$ and the CS gain $[eqn]$ of three gain-boosting stages with x from 5 to 7.

In the conventional RGC TIA design, the dominant pole is restricted by large PD parasitic capacitance $[eqn]$ at the input node. In contrast, as the single-stage cascode feedback further reduces the input impedance $[eqn]$ of the RGC input stage, the dominant pole $[eqn]$ of the proposed TIA circuit is located at the drain of $[eqn]$ instead, which is shown as

$$[eqn]$$

where $[eqn]$ is the sum of gate parasitic capacitance of $[eqn]$ .

The bandwidth-extension stage with capacitive degeneration is to compensate the dominant pole with a zero at ( $[eqn]$ )^−1^, which requires

$$[eqn]$$

As $[eqn]$ is constant for pole-zero compensation, a relatively large $[eqn]$ with a small $[eqn]$ can be chosen to push $[eqn]$ (i.e., $[eqn]$ generated by the capacitive degeneration) to a higher frequency to prevent $[eqn]$ from bandwidth determination.

Therefore, as the dominant pole is compensated in the bandwidth-extension stage, the second lowest pole with the largest capacitance in the gain-boosting and buffer stages determines the −3 dB bandwidth. In the following CS stages, each stage contributes a pole at its output node, as described by

$$[eqn]$$

where $[eqn]$ and $[eqn]$ , respectively, refer to the load resistor and the lumped capacitance at the drain of the CS transistor $[eqn]$ with x from 5 to 8.

Based on the aforementioned analysis of zero and poles, the frequency response of proposed TIA design is illustrated in Figure 4. As the frequency increases, the $[eqn]$ first encounters $[eqn]$ and $[eqn]$ . Since the pole at $[eqn]$ is compensated by the zero at $[eqn]$ , $[eqn]$ remains constant. Then, when $[eqn]$ exceeds $[eqn]$ , $[eqn]$ decreases with a slope of 20 dB/dec. In the three CS stages, as the load resistors satisfy $[eqn]$ , thus, $[eqn]$ . Therefore, when $[eqn]$ exceeds $[eqn]$ , $[eqn]$ further decreases with a slope of 40 dB/dec. When $[eqn]$ exceeds $[eqn]$ and $[eqn]$ , $[eqn]$ continues to decrease with a slope of 80 dB/dec. Combining Equations (13)–(16), the transfer function of the proposed TIA can be described as

$$[eqn]$$

As the lumped capacitance of the NMOS transistors in 40 nm CMOS is less than one-tenth of the load capacitance (150 fF), the second lowest pole of the proposed TIA is located at the output node, which determines the −3 dB bandwidth as described by

$$[eqn]$$

where $[eqn]$ is the drain parasitic capacitance of $[eqn]$ , and $[eqn]$ is the output load capacitance.

2.5. Noise Analysis

To simplify the analysis, the noise contribution of the stages subsequent to the cascode-feedback RGC input stage is neglected, as their noise is attenuated by the gain of input stage $[eqn]$ when referred to input.

In the cascode-feedback RGC input stage, the noise sources mainly come from the common-gate amplifier ( $[eqn]$ ) and the cascode feedback amplifier ( $[eqn]$ ). In general, these device noises are uncorrelated and can be added directly. As a cascaded transistor in the single-stage cascode structure, $[eqn]$ adds no extra noise to the circuit, whose noise contribution is neglected in the following noise analysis. By analyzing the noise sources in the RGC structure, the input-referred noise of the proposed TIA can be expressed as

$$[eqn]$$

where $[eqn]$ , $[eqn]$ , $[eqn]$ , $[eqn]$ , $[eqn]$ , K is Boltzmann constant, T is the absolute temperature, $[eqn]$ is the noise factor of MOSFET device. $[eqn]$ and $[eqn]$ are derived in Equations (2) and (3), respectively.

From Equation (19), the first term $[eqn]$ is the frequency-independent noise component contributed by $[eqn]$ , which is directly added to the input node. The second term, i.e., the noise contribution of $[eqn]$ is extremely small at low frequencies yet increases rapidly with frequency. At high frequencies, the major noise contributors are $[eqn]$ , $[eqn]$ , and $[eqn]$ , with the growth rate primarily determined by the total capacitance at the input node as elaborated in Equation (3). According to (19), the values of $[eqn]$ , $[eqn]$ , and $[eqn]$ are designed to be as large as possible while still guaranteeing the voltage headroom. And the value of $[eqn]$ is set considering both noise and bandwidth. Thanks to the proposed design strategy under low supply voltage in Section 2.2, the value of $[eqn]$ is enabled to be larger at the same current consumption for better noise efficiency.

3. Simulation Results and Comparison

Based on the above analysis in Section 2, Table 2 lists the sizing of MOSFET devices in the proposed TIA circuit, which are carefully designed for optimizing the trade-off among bandwidth, gain, and noise performance. The proposed prototype circuit was simulated and analyzed with these dimensions.

Figure 5 shows the layout design in 40 nm CMOS technology, and the core area is 0.004 mm^2^. The proposed TIA design is simulated under a 1.2 V supply. The proposed TIA consumes 10.4 mW total power, of which the RGC input stage, capacitive degeneration stage, three CS stages, and output buffer stage account for 1 mW, 1.4 mW, 4.2 mW, and 3.8 mW, respectively. In the first stage, the CS transistor $[eqn]$ is biased in weak inversion for improved power efficiency; therefore, the input stage does not consume high power. The capacitive degeneration stage extends the bandwidth with passive components, i.e., capacitors, thus featuring low power consumption. The three CS stages and output buffer consume more power to boost gain and driving capability, accounting for 40% and 37% of the total energy consumption, respectively. Thanks to the design strategy of the RGC TIA in the 40 nm CMOS process, the proposed TIA consumes 8~72% less power compared with existing 10 GB/s TIA designs in the literature [16,18,23,24,25,26].

Figure 6 exhibits the four output node transimpedance responses of the cascode-feedback RGC input stage, capacitive degeneration stage, gain-boosting stage, and output buffer stage from 1 MHz to 20 GHz. As shown in the figure, the proposed TIA achieves a total transimpedance gain of 71 dBΩ from 1 MHz to the high-frequency range. The transimpedance gains simulated at the output nodes of the RGC input stage, capacitive degeneration stage, three CS stages, and output buffer stage are 53.7 dBΩ, 52.3 dBΩ, 72.5 dBΩ, and 71 dBΩ, respectively. Under the constraint of voltage headroom, $[eqn]$ (520 Ω) provides the transimpedance gain of 53.7 dBΩ at the output node of the RGC input stage. Then the capacitive degeneration deteriorates gain by 1.4 dB, trading for a significant bandwidth extension. Therefore, the subsequent three gain-boosting stages increase gain from 52.3 dBΩ to 72.5 dBΩ via the gain product of $[eqn]$ . Lastly, the output buffer stage is designed to achieve 50 Ω impedance matching, which results in a 1.5 dBΩ reduction in the overall gain. The result is consistent with the analysis of Equation (13). The proposed TIA achieves an 18 dB~30 dB improvement compared with the existing RGC TIA designs in [18,23,24,25,26], thanks to the help of $[eqn]$ and three CS stages in our design.

Figure 6 shows that the proposed TIA achieves a −3 dB bandwidth of 9.2 GHz with 0.15 pF PD capacitance and 0.15 pF load capacitance $[eqn]$ . The simulated −3 dB bandwidths at the output nodes of the RGC input stage, capacitive degeneration stage, three CS stages, and output buffer stages are 10.6 GHz, 12.3 GHz, 10 GHz, and 9.2 GHz, respectively. As the single-stage cascode feedback effectively reduces the input impedance $[eqn]$ , the dominant pole is no longer restricted by the large $[eqn]$ at the input node. In contrast, the bandwidth of the RGC input stage is determined by $[eqn]$ and the parasitic capacitance at the output node. The capacitive degeneration introduces a zero for pre-equalization, further extending the bandwidth from 10.6 GHz to 12.3 GHz, i.e., an enhancement ratio of 1.16. Then, the three CS stages degrade the bandwidth with three poles located at their output nodes, and the output buffer also reduces the bandwidth with the second lowest pole induced by $[eqn]$ . The result is consistent with the analysis of frequency response in Section 2.4. Owing to the single-stage cascode feedback and capacitive degeneration techniques, the proposed TIA outperforms the inverter-based TIAs in [16] and RGC TIAs in [18,23] in terms of bandwidth, by 1.8× and 1.15×~1.3×, respectively.

Figure 7 exhibits the bandwidths of the proposed TIA with different $[eqn]$ values at the input node. As $[eqn]$ triples from 50 fF to 150 fF, the bandwidth of the proposed TIA decreases from 10.7 GHz to 9.2 GHz, only a reduction of 14%. As $[eqn]$ doubles from 150 fF to 300 fF, the bandwidth of the proposed TIA decreases from 9.2 GHz to 7.1 GHz, representing a 23% reduction. In contrast, for conventional TIA circuits, the bandwidth would decrease by 50% when $[eqn]$ doubles. Thanks to the single-stage cascode feedback structure, the impact of the input node on bandwidth is effectively mitigated.

To evaluate the process, voltage, and temperature (PVT) variation effects on the proposed TIA, Figure 8 exhibits the transimpedance response of the proposed TIA under three process corners, ±0.1 V of supply voltage variation, and temperature ranging from −20 °C to 60 °C. As illustrated in Figure 8a, the proposed TIA at the ff corner achieves a bandwidth of 12 GHz and a gain of 60 dBΩ. This is attributed to the reduced resistance at the ff corner, thereby increasing the pole frequencies in the TIA circuit. However, the abnormal gain and bandwidth performance at the ss corner are mainly due to increased resistances, which raise the gain of the front-end stages of the proposed TIA, thereby driving the final-stage OB into cut-off operation. This performance degradation caused by process variations can be optimized via the trimming technique, which will be added in our future tape-out. Figure 8b exhibits, for ±0.1 V of supply voltage variation, the transimpedance gain and −3 dB bandwidth changes for 7.1 dBΩ and 1.6 GHz, respectively. The increase of supply voltage results in a higher transimpedance gain and an extended bandwidth. Higher supply voltage produces more current passing through each of the five stages of the proposed TIA for the same $[eqn]$ , which enhances $[eqn]$ and thereby boosts the gain and bandwidth as analyzed in Section 2. Figure 8c depicts that for 80 °C variations over temperature, the transimpedance gain and −3 dB bandwidth changes for 4.4 dBΩ and 1.5 GHz, respectively. The increase in temperature results in higher resistances, thereby enhancing the transimpedance gain while decreasing the bandwidth of the proposed TIA. Thanks to the careful design of the sizes and parameters of the critical devices in Section 2, the transimpedance response of the proposed TIA has small variations across different supply voltage and temperature conditions.

Under PVT variations, although the transconductance (g_m_) variations of the common-gate input transistor g_m1_ and the common-source feedback transistor g_m2_ in the RGC input stage are a little bit large, the gain of the RGC input stage is primarily determined by $[eqn]$ in (1), whose variation is not significant. According to (2) and (5), the g_m_ values of the transistors primarily affect the input resistance $[eqn]$ of the RGC input stage, thereby influencing the bandwidth, as shown in (3). Across three process corners, with the supply voltage ranging from 1.1 V to 1.3 V and the temperature spanning −20 °C to 60 °C, $[eqn]$ remains below 100 Ω and S11 is below −10 dB. Therefore, gm variations do not result in significant degradation of gain or bandwidth.

To conduct the best cases and worst cases of PVT variations, Figure 9 exhibits the post-simulated PVT analysis for the transimpedance response of the proposed TIA. The best case of PVT variations occurs at the ff process corner, under the conditions of a 1.3 V supply voltage and a temperature of −20 °C. The proposed TIA achieves a bandwidth of 14.1 GHz and a gain of 60.5 dBΩ. The worst case of PVT variations occurs at the ss process corner, under the conditions of a 1.1 V supply voltage and a temperature of −20 °C, where the TIA exhibits no gain at all. The abnormal transimpedance response at the ss corner is mainly due to increased poly-silicon resistances, which raise the gain of the front-end stages of the proposed TIA, thereby driving the final-stage OB into cut-off operation.

As shown in Figure 10, this performance degradation caused by process variations can be optimized via the trimming circuits. In the three gain-boosting CS stages, the original load resistors $[eqn]$ and $[eqn]$ in Figure 2 are actually implemented by $[eqn]$ in series with $[eqn]$ , and $[eqn]$ in series with $[eqn]$ , with their values set to (20a) and (20b), respectively.

$$[eqn]$$ $$[eqn]$$

Then, $[eqn]$ and $[eqn]$ are shunted by PMOS switches $[eqn]$ and $[eqn]$ , respectively. When the circuit is operating well at the ff and tt process corners, Vc is set to the supply voltage, turning off the switches, and the load resistance values remain equal to the original values of $[eqn]$ and $[eqn]$ , respectively. When the circuit operates at the ss process corner, Vc is set to ground, turning on the switches and shorting $[eqn]$ and $[eqn]$ , resulting in the load resistance values being halved compared to the original $[eqn]$ and $[eqn]$ . This maintains a sufficiently high drain voltage for $[eqn]$ and $[eqn]$ , ensuring that all subsequent transistors operate in the saturation region.

To evaluate the impact of switches on the performance of the proposed TIA circuit, Figure 11 exhibits the post-simulated PVT analysis for the transimpedance response of the proposed TIA with the trimming technique. When simulated at the tt and ff process corners, the PMOS switches are turned off by setting Vc to the supply voltage. The best case of PVT variations occurs at the ff process corner, under the conditions of a 1.3 V supply voltage and a temperature of −20 °C. The proposed TIA achieves a bandwidth of 13.5 GHz and a gain of 60.5 dBΩ. When simulated at the ss process corner, the PMOS switches are turned on by setting Vc to ground. The worst case of PVT variations occurs at the ss process corner, under the conditions of a 1.1 V supply voltage and a temperature of 60 °C. The proposed TIA achieves a bandwidth of 6.4 GHz and a gain of 72.8 dBΩ. Since a bandwidth is about 60~70% of the data rate as recommended for high-speed TIAs [30], the worst-case bandwidth of the proposed TIA can still meet the requirements of 10 Gb/s applications.

Figure 12 presents the input-referred noise current spectral density of the proposed TIA from 100 MHz to 100 GHz. The input-referred noise current can be calculated by dividing the integrated output noise voltage by the TIA’s transimpedance gain, as exhibited by

$$[eqn]$$

where $[eqn]$ represents the equivalent noise bandwidth (ENBW) of the proposed TIA. For typical single-pole low-pass filter systems, $[eqn]$ is $[eqn]$ times the −3 dB bandwidth $[eqn]$ . Accordingly, the calculated input-referred noise current $[eqn]$ is 1.76 $[eqn]$ A within the integral range from 100 MHz to 14.5 GHz. Therefore, the average input-referred noise current density can be derived as

$$[eqn]$$

The calculated average input-referred noise is about 18.3 $[eqn]$ . In the proposed design, the single-stage cascode feedback, capacitive degeneration, and gain-boosting techniques are adopted to enhance the bandwidth and gain while minimizing the noise. Thanks to the noise analysis as derived in Section 2.5, the sizing of the noise-critical devices in the proposed TIA is carefully optimized for noise reduction. The noise performance of the proposed TIA design is about 40~61% better than the existing RGC TIA designs in [23,24,25,26]. Compared with [18], this work achieves comparable noise performance with a higher bandwidth and wider integration range.

To further verify the impact of process variation, Figure 13 exhibits a 200-iteration Monte-Carlo simulation for −3 dB bandwidth and average input-referred noise. Figure 13a indicates the worst-case value of the bandwidth is 9.16 GHz. The standard deviation of the Monte-Carlo simulation results is 42.3 MHz, which is smaller than 1% of 9.25 GHz, the mean value of the −3 dB bandwidth of the proposed TIA. Figure 13b shows the worst-case value of the input-referred noise is 18.6 $[eqn]$ . The standard deviation of the Monte-Carlo simulation results is 80.55 $[eqn]$ , which is smaller than 1% of 18.33 $[eqn]$ , the mean value of the average input-referred noise of the proposed TIA. Thanks to the careful design of the sizes and parameters of the critical devices in Section 2, a robust broad-bandwidth and noise performance of the proposed TIA subject to the process variation is achieved.

Figure 14 depicts the output eye diagram of the proposed TIA with a 10 Gb/s 2^31^-1 pseudorandom binary sequence (PRBS) for different input currents. The 100 ps eye width aligns with the period of the 10 Gb/s signal. The eyes are opened at 88 mV, 324 mV, 529 mV for 10 Gb/s pseudo-random input currents of 25 μA, 100 μA, and 200 μA, respectively. Hence, the proposed TIA provides the input current dynamic range of 18 dB for 10 Gb/s applications. In terms of the dynamic range, its lower limit is determined by noise and signal-to-noise ratio (SNR), while its upper limit is reached when the signal approaches saturation. The calculated input-referred noise current of this work is 1.76 μA. To meet a bit error rate (BER) of 10^−12^, the SNR must be greater than 14, leading to a lower limit of 25 μA peak-to-peak current (Ipp) for the input dynamic range. When Ipp is 200 μA, the upper edge of the eye flattens, which equals the supply voltage, as shown in Figure 14, thus defining the upper limit of the dynamic range. The relatively narrow dynamic range is mainly attributed to the high gain of this work. As this work is a study of pre-TIA, for a specific application requiring higher dynamic range, variable gain technology can be incorporated to make a more complete AFE design to further expand the input dynamic range.

The waveform in Figure 14 shows the proposed TIA circuit exhibits a wide-open, distortion-free eye, which indicates a good signal quality. Since a bandwidth is about 60~70% of the data rate as recommended for high-speed TIAs [30], the bandwidth requirement of 10 Gb/s applications is approximately 7 GHz. The signal quality improvement of this design is primarily attributed to cascode feedback and capacitive degeneration, which reduce $[eqn]$ and further extend bandwidth, respectively. The achieved bandwidth of 9.2 GHz is 1.3 times higher than the requirement for 10 Gb/s applications, providing a sufficient design margin for the 10 Gb/s specification.

Figure 15 shows the impedance matching performance of the proposed TIA across the frequency range of 100 MHz to 100 GHz, where S11 and S22 denote the reflection coefficients at the TIA’s input and output ports, respectively. The points on the S-parameter curves indicate the simulated $[eqn]$ and $[eqn]$ values at 100 MHz are lower than −15 dB and −20 dB, respectively. S11 and S22 remain less than −5 dB and −10 dB over the −3 dB bandwidth of 9.2 GHz. As the input and output resistance is designed to be 50 Ω, the proposed TIA exhibits excellent impedance matching performance, ensuring efficient signal transmission with minimal reflection loss.

Figure 16 depicts the simulated input and output resistance from 100 MHz to 100 GHz. Figure 16a shows the input resistance of the proposed TIA is 64.4 Ω at 100 MHz and 92 Ω at 9.2 GHz. This performance achievement benefits from the single-stage cascode feedback in the RGC input stage, which increases the input node pole frequency and reduces the impact of the large $[eqn]$ at the input node on bandwidth restriction, as compared to the existing inverter-based TIA works. Figure 16b indicates the output resistance of the proposed TIA remains lower than 60 Ω over the −3 dB bandwidth of 9.2 GHz. This performance improvement is mainly due to the output buffer, whose load resistor $[eqn]$ is specifically designed to be 60 Ω for impedance matching. Furthermore, the low output resistance also boosts the second lowest pole frequency, thus extending the overall bandwidth.

Table 3 compares the performance of the proposed TIA design against prior designs in the literature. For a fair comparison, the Figure of Merit (FOM) employed here is the FOM widely used in [16,31] that is normalized by supply voltage (V), as depicted by

$$[eqn]$$

As shown in Table 3, the proposed inductorless design achieves a notably higher FOM of 48.6, reaching 25 dB higher gain, 61% lower noise, and 72% lower power than the state-of-the-art design [26]. This is because the combination techniques of single-stage cascode feedback, capacitive degeneration, and gain boosting relax the stringent trade-off among bandwidth, gain, and noise in advanced CMOS processes. Compared to the inverter-based TIA designs in [16], this work achieves almost the same FOM while consuming 8% less power. Compared with [18], this work achieves comparable noise performance with superior bandwidth, gain, and power. The proposed RGC TIA possesses a 7.4×~243× higher FOM with lower noise and power consumption against the prior RGC TIA designs in [23,24,25,26].

4. Conclusions

This paper presents a novel RGC TIA design that achieves high bandwidth, low input-referred noise, and low power consumption in an advanced CMOS process. Through the combination of single-stage cascode feedback, capacitive degeneration, and gain-boosting technologies, the proposed RGC TIA significantly enhances the −3 dB bandwidth while reducing noise and power consumption, which is suitable for emerging optical applications such as Lidar, short-range optical communication, and optical integrated sensing and communication.