# A Low-Noise, Low-Power, and Wide-Bandwidth Regulated Cascode Transimpedance Amplifier with Cascode-Feedback in 40 nm CMOS

## TL;DR

This paper introduces a new transimpedance amplifier design for optical applications that achieves high bandwidth, low noise, and low power consumption in 40 nm CMOS.

## Contribution

A novel regulated cascode TIA with cascode-feedback is proposed, offering improved bandwidth, noise reduction, and power efficiency.

## Key findings

- The proposed TIA achieves a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ.
- The design consumes only 6.6 mW at 1.2 V, excluding the output buffer.
- It provides a 7.4× to 243× improvement in figure of merit compared to prior RGC TIA designs.

## Abstract

The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/Hz. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit.