SiC Double-Trench MOSFETs with an Integrated MOS-Channel Diode for Improved Third-Quadrant Performance

TL;DR

A new SiC MOSFET design with an integrated diode improves performance by reducing voltage and resistance while maintaining breakdown voltage.

Contribution

A novel double-trench SiC MOSFET with an integrated MOS-channel diode is proposed to enhance third-quadrant performance.

Findings

The cut-in voltage Von is reduced by 69.2% due to the drain-induced barrier-lowering effect.

The specific on-resistance Ron,sp is lowered by reducing the p-well region and the JFET effect.

Switching loss increases slightly due to higher gate charge Qg.

Abstract

In this article, a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD) is proposed and analyzed through TCAD simulations. The MCD incorporates a short channel, where the channel length can be adjusted by modifying the recess depth. Owing to the drain-induced barrier-lowering (DIBL) effect, a low potential barrier is created for electrons flowing from the JFET region to the N+ source region. This effectively eliminates the bipolar degradation of the parasitic body p-i-n diode and reduces the cut-in voltage Von by 69.2%. Additionally, the breakdown voltage (BV) remains nearly unchanged. The reduction in the p-well region alleviates the JFET effect, successfully lowering the specific on-resistance Ron,sp, making the channel easier to turn on, and reducing the threshold voltage (Vth). However, the increase in the gate charge Qg results in a slight rise in the switching loss.

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Full text

1. Introduction

Silicon carbide (SiC) is distinguished by its superior material properties, including a higher breakdown electric field strength and a larger bandgap, which enable the development of devices with ultra-low on-state resistance and outstanding switching characteristics. These advantages make SiC one of the most attractive wide-bandgap semiconductor materials for power electronics applications [1,2]. Additionally, these properties make SiC particularly well suited for applications that require high power density and efficiency in power conversion [3,4]. In many applications, the body diode of a MOSFET plays a crucial role by functioning as a freewheeling diode, as is commonly seen in voltage source inverters [5]. In most power converter circuits, the output power is regulated by the alternating conduction of the switch and the freewheeling diode, which, in turn, carries the load current. Due to the cost advantages of the system, the prospect of using the intrinsic body diode of the MOSFET as the freewheeling diode in these applications is particularly attractive [6]. However, the parasitic body diode of the SiC MOSFET is unsuitable for use in many applications for two reasons. First, the wide bandgap of SiC results in a high turn-on voltage ( $[eqn]$ ) for its body diode, leading to increased switching loss [7,8]. Second, bipolar degradation, a widely acknowledged issue, is caused by the formation of stacking faults (SFs) and has an adverse effect on long-term reliability [9,10].

To address the aforementioned problems, SiC MOSFETs with embedded unipolar diodes have been proposed. These designs enhance reverse conduction performance by achieving a low $[eqn]$ while effectively eliminating bipolar degradation. One notable approach involves integrating junction barrier Schottky (JBS) diodes or Schottky barrier diodes (SBD) into SiC MOSFETs, as demonstrated in several studies [11,12,13,14,15,16,17]. However, JBS and SBD diodes exhibit much higher leakage currents, particularly under high-temperature operating conditions [18,19]. A SiC MOSFET with an integrated heterojunction diode has been proposed and studied as a potential alternative [20,21,22,23]. However, this approach entails a complex and challenging manufacturing process and may lead to an increased electric field at the heterojunction interface [24]. The integration of the normally OFF JFET diode with the SiC MOSFET has also been proposed and investigated [25,26]. However, the electrical characteristics of the normally OFF JFET diode are quite sensitive to the mesa width [27]. An SiC MOSFET with an integrated MOS-channel diode (MCD) has also been proposed [28]. However, due to the presence of oxide on the bottom trench surface, the P+ region at the bottom of the source-contact trench remains floating.

In this article, a double-trench MOSFET (DTMOS) with an integrated MOS-channel diode (MCD), which improves reverse conduction performance, is proposed and demonstrated through TCAD simulations. Compared to the conventional SiC DTMOS, the proposed structure eliminates bipolar degradation and exhibits superior reverse conduction performance with almost no impact on other device characteristics.

2. Device Structure and Mechanism

The schematic cross-sections of the conventional SiC DTMOS and the proposed MOSFET are shown in Figure 1a,b. In both SiC MOSFETs studied, a grounded P+ shield region under the recessed source is implemented to shield the field near the gate bottom from high electric fields. The key distinction from the previously proposed SiC MOSFET [28] is that the P+ region at the bottom of the source-contact trench is grounded rather than floating, which also simplifies the fabrication process. At the same time, it reduces the JFET effect caused by the addition of a P-well region at the bottom of the gate trench, achieving a good trade-off between breakdown voltage (BV) and $[eqn]$ . Compared to the conventional DTMOS, the proposed MOSFET incorporates an MCD consisting of N+, P-base, and N-drift regions, achieved by forming an oxide layer along the sidewalls of the source trench. The main device parameters used in the simulation are listed in Table 1.

Figure 2 shows the impact of the channel length $[eqn]$ on both the cut-in voltage $[eqn]$ and the breakdown voltage (BV) in the proposed SiC MOSFET. As shown, the breakdown voltage remains almost constant across various values of $[eqn]$ , with only a slight change observed when $[eqn]$ is reduced to 0.2 $[eqn]$ m. This indicates that the breakdown voltage is largely unaffected by changes in channel length until it reaches 0.1 $[eqn]$ m. On the other hand, the cut-in voltage $[eqn]$ exhibits a noticeable decrease as $[eqn]$ is reduced. Specifically, when $[eqn]$ is reduced from 0.5 $[eqn]$ m to 0.2 $[eqn]$ m, $[eqn]$ decreases from 1.6 V to 0.8 V, representing a 69.2% reduction compared to the conventional structure. Notably, the breakdown voltage (BV) remains almost unchanged, which suggests that the device’s overall voltage withstand capability is preserved even with the reduction in channel length, making this design approach highly efficient for achieving lower cut-in voltage without compromising the breakdown voltage.

This behavior is attributed to the continuous reduction in the potential barrier, as shown in Figure 3. The electron potential barrier decreases with the reduction in $[eqn]$ , a phenomenon driven by the drain-induced barrier-lowering (DIBL) effect, as demonstrated in the experimental works of [30,31]. As the channel length shortens, the barrier that electrons must overcome to flow from the source to the drain is significantly lowered, which, in turn, reduces the cut-in voltage $[eqn]$ . As shown in Figure 3, reducing $[eqn]$ from 0.5 to 0.2 $[eqn]$ m decreases the electron potential barrier by 0.9 eV, which, in turn, lowers the $[eqn]$ of the MOSFET. This reduction allows the proposed SiC MOSFET to achieve a significantly lower cut-in voltage with minimal adjustments to the device structure. Based on this trade-off, $[eqn]$ $[eqn]$ m is selected for further analysis, as it offers a good balance between the desired reduction in $[eqn]$ and the stability of the breakdown voltage.

Figure 4 presents the transfer characteristics of the conventional SiC DTMOS, the previously proposed SiC MOSFET, and the newly proposed SiC MOSFET. Although the previous MOSFET offers comparable advantages in electrical performance and reliability to the new MOSFET, its structural differences enable it to exhibit the small mesa effect. As a result, the mesa between the P+ shield regions is relatively narrow, causing the threshold voltage ( $[eqn]$ ) to increase from 2.1 V to 3.3 V, which is a 57% increase. In addition, compared to the conventional DTMOS, the reduction in the area of the P+ region results in a decrease in $[eqn]$ from 2.3 V to 2.1 V, which is a reduction of 8.7%.

Figure 5 shows the forward conduction characteristics of the conventional SiC DTMOS and the proposed SiC MOSFET. From the curves, the $[eqn]$ values of the conventional DTMOS and the proposed SiC MOSFET are calculated to be 1.427 m $[eqn]$ ∗cm^2^ and 1.209 m $[eqn]$ ∗cm^2^, respectively, indicating a 15% reduction in $[eqn]$ for the proposed structure. This improvement underscores the enhanced performance of the proposed MOSFET compared to the conventional DTMOS. The reduction in $[eqn]$ is primarily attributed to the reduction in the P-well region, which effectively alleviates the JFET effect, contributing to lower resistance.

In this study, Sentaurus TCAD tools are used to perform the device simulations and the mixed-mode simulations. The detailed parameters of the cell are provided in Table 1. Several critical models are incorporated [27], including Shockley–Read–Hall recombination, Auger recombination, the Okuto–Crowell model for BV simulations, incomplete ionization, doping-dependent transport, bandgap narrowing, barrier lowering, and anisotropic material properties. Additionally, mobility models considering doping dependence, high-field saturation, and the normal effect are included. Acceptor and donor traps in the P-type region, as well as contact resistance, are included as key factors in suppressing the body diode current during third-quadrant conduction, as reported in [30]. The SiC/SiO_2_ interface trap density is set to $[eqn]$ [28].

3. Simulation Results and Discussion

Figure 6 shows the reverse conduction characteristics of both the conventional DTMOS and the proposed SiC MOSFET at $[eqn]$ V. In the conventional DTMOS, the body diode was responsible for conducting the reverse current, with a cut-in voltage $[eqn]$ of 2.6 V ( $[eqn]$ ). In the conventional structure, the source-drain current $[eqn]$ was primarily composed of the hole current, which led to bipolar degradation. Bipolar degradation can result in stacking faults and other reliability issues, severely compromising the device’s performance. Therefore, it was crucial to mitigate or eliminate this effect to ensure device reliability and performance. In the proposed MOSFET, when $[eqn]$ was reduced from 0.5 to 0.2 $[eqn]$ m, $[eqn]$ decreased from 1.6 V to 0.8 V. This reduction is attributed to the drain-induced barrier-lowering (DIBL) effect, which is illustrated in Figure 3. Compared to the conventional DTMOS, $[eqn]$ was reduced by 69.2%. More importantly, in the proposed SiC MOSFET, the conduction current $[eqn]$ was carried by electrons instead of holes. This change effectively eliminated the bipolar degradation seen in conventional DTMOS devices. By replacing hole conduction with electron conduction, the proposed MOSFET avoids the reliability issues associated with bipolar degradation, thus ensuring better overall performance, enhanced reliability, and a longer operational lifespan.

Figure 7a shows the hole current distribution at $[eqn]$ in the conventional DTMOS, highlighting the presence of hole current flowing through the P-base region. In contrast, Figure 7b shows the hole current distribution in the proposed MOSFET, where it is evident that no hole current flowed through the P-base region. Further analysis of the total current density distributions at $[eqn]$ is presented in Figure 8a,b for the conventional DTMOS and the proposed MOSFET, respectively. From these figures, it is clear that in the proposed SiC MOSFET, the MOS-channel diode was turned on. As a result, all reverse conduction current was carried out by the MOS-channel diode, preventing the flow of current through the body diode. This observation confirms that the body diode in the proposed structure was completely deactivated, effectively eliminating the risk of bipolar degradation. This represents a significant improvement over the traditional DTMOS structure.

The electric field distributions at $[eqn]$ for the two studied SiC MOSFETs are shown in Figure 9. In MOSFETs, the electric field is typically concentrated near the gate oxide, especially at the corners of the trench, which can lead to significant reliability concerns. This is because, in the rounded corners of the trench, where the curvature is lower, the electric field lines tend to concentrate more densely, resulting in the highest electric field strength in these regions. Consequently, the maximum electric field in each device occurred in the gate oxide at the trench corners. Despite modifications to the source trench and a reduction in the p-well area, the $[eqn]$ in the proposed MOSFET showed almost no degradation compared to the conventional DTMOS. Most of the electric field in the gate oxide was below the safety limit (4 MV/cm [8]), ensuring the long-term reliability of the gate oxide.

Figure 10 illustrates the behavior of the conventional SiC DTMOS and the proposed SiC MOSFET at different temperatures. At 300 K, the breakdown voltage of the proposed structure was nearly identical to that of the conventional structure. However, when the temperature rose to 450 K, the leakage current in the proposed structure increased significantly due to a reduction in the potential barrier. Despite the increase in the leakage current, the breakdown voltage of the proposed structure remained almost the same as it was at 300 K.

A comparison of the capacitance characteristics of the two studied SiC MOSFETs is shown in Figure 11. The input capacitance ( $[eqn]$ ) and output capacitance ( $[eqn]$ ) were nearly identical for both devices. The feedback capacitance ( $[eqn]$ or $[eqn]$ ), however, was slightly larger for the proposed MOSFET than for the conventional DTMOS. Figure 12b shows the gate charge characteristics of the conventional DTMOS and the proposed SiC MOSFET. The gate–drain charge ( $[eqn]$ ) was observed within the plateau region of the gate charge curve. The extracted $[eqn]$ values were 327 nC/cm^2^ for the conventional DTMOS and 346 nC/cm^2^ for the proposed SiC MOSFET. An increase in $[eqn]$ , caused by parasitic capacitance between the gate and drain, resulted in extended switching times. Although the $[eqn]$ of the proposed structure increased slightly by 5.8%, its $[eqn]$ was reduced. As a result, the high-frequency figure of merit (HF-FOM), defined as $[eqn]$ , was calculated to be 466.6 m $[eqn]$ ·nC for the conventional DTMOS and 418.3 m $[eqn]$ ·nC for the proposed structure. This represents a 10.4% reduction in the HF-FOM for the proposed structure compared to the conventional DTMOS, indicating its improved performance in high-frequency applications.

The switching characteristics of the conventional DTMOS and the proposed SiC MOSFET were evaluated using the double-pulse test circuit illustrated in Figure 13a. The switching waveforms are presented in Figure 13b, while Figure 14 provides a comparative analysis of the switching losses for both devices. It can be observed that the current and voltage waveforms during the first turn-on and turn-off were almost identical for the conventional DTMOS and the proposed structure. As a result, the turn-on and turn-off losses were nearly the same for both devices. However, due to the slightly higher $[eqn]$ of the proposed structure compared to the conventional DTMOS, the total switching loss increased by 7% (from 0.67 to 0.72 mJ/cm^2^). However, during the second turn-on, it can be observed that the drain current ( $[eqn]$ ) of the proposed MOSFET settled oscillations more quickly than that of the conventional DTMOS. This is because the proposed MOSFET integrates a MOS-channel diode, which provides a faster reverse recovery speed, resulting in a quicker current recovery compared to the conventional DTMOS.

Table 2 presents a comparison of the key characteristics between the conventional DTMOS and the proposed SiC MOSFET. The proposed SiC MOSFET demonstrated improved performance, mainly due to the integration of the MCD structure. The reduced size of the bottom p-well in the proposed MOSFET resulted in a smaller depletion region, which, in turn, increased the current-carrying region when the device was in operation. This design effectively led to a significant reduction in $[eqn]$ . Moreover, the threshold voltage ( $[eqn]$ ) of the device was determined by the size of the depletion region and the current flowing through the device.

4. Conclusions

In this article, a novel SiC double-trench MOSFET with an integrated MCD is proposed and simulated in Sentaurus TCAD. Due to the drain-induced barrier-lowering (DIBL) effect, the electron potential barrier is reduced by decreasing $[eqn]$ . As the channel length shortens, the barrier that electrons must overcome to flow from the source to the drain is significantly lowered, which, in turn, reduces the cut-in voltage ( $[eqn]$ ) and prevents current from flowing through the body diode. This effectively eliminates the risk of bipolar degradation. Furthermore, the breakdown voltage (BV) remains almost unchanged, while the switching loss only increases to 0.67 mJ/cm^2^ for the conventional DTMOS and to 0.72 mJ/cm^2^ for the proposed SiC MOSFET. The proposed structure not only eliminates bipolar degradation but also exhibits superior reverse conduction performance with minimal impact on other device characteristics. These advantages position the proposed SiC MOSFET as a strong competitor for power electronic applications.