A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs (English Version)

TL;DR

This paper introduces a digitally controllable CMOS LNA architecture that adjusts gain and power to improve yield and performance amidst process variations, maintaining low power consumption.

Contribution

It proposes a novel architecture for CMOS LNAs with digital control for gain and power, enhancing yield and robustness against process variations.

Findings

Achieved yield improvement with the proposed architecture.

Maintained low-power operation comparable to traditional LNAs.

Validated the approach with a 130 nm CMOS LNA design.

Abstract

This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI{130}{nm}, \SI{1.2}{V} LNA implementing the proposed architecture is designed based on an analysis of variability in traditional LNAs under different bias currents and on the corresponding effects on the performance of a complete receiver. Two different adjustment strategies are evaluated, both of which are compatible with previously reported built-in self-test (BIST) circuits. Results show that the proposed architecture enables yield enhancement while keeping low-power operation compared with traditional LNAs.

Tables

Table 1. TABLE I: LNA specifications (matching at 50   Ω 50\text{\,}\mathrm{\SIUnitSymbolOhm} ).

Frequency	$2.4$–$2.5\mathrm{GHz}$
Gain $G$	$10.5\pm 0.5$ dB
Noise figure (NF)	dB
IIP3	$>-4$ dBm
$S_{11}$, $S_{22}$	dB

Table 2. TABLE II: Sizing of the selected LNAs.

Parameter	$I_{NOM}$ (mA)
	0.4	0.5	0.6	0.7
$W_1/L_1$ ($\mu$m/$\mu$m)	40/0.12	56/0.12	64/0.12	80/0.12
$L_s$ (nH)	2.51	2.51	2.51	2.65
$L_g$ (nH)	11.8	7.40	6.06	5.02
$C_X$ (fF)	246	383	453	532
$C_1$ (fF)	439	429	425	416
$C_P$ (pF)	1.71	1.62	1.61	1.54
$L_D$ (nH)	10.5	10.5	10.5	10.5

Table 3. TABLE III: Mean and worst-case values from Monte Carlo (traditional LNAs).

	$I_{NOM}=0.4\mathrm{mA}$			$I_{NOM}=0.5\mathrm{mA}$			$I_{NOM}=0.6\mathrm{mA}$			$I_{NOM}=0.7\mathrm{mA}$
Parameter	min	mean	max	min	mean	max	min	mean	max	min	mean	max
$G$ (dB)	8.64	10.4	11.7	8.23	10.4	11.6	8.92	10.5	11.6	8.67	10.4	11.4
NF (dB)	–	2.8	–	–	2.8	–	–	2.7	–	–	2.7	–
IIP3 (dBm)	-10.4	0.7	–	-9.6	4.2	–	-6.6	5.4	–	-5.8	5.4	–
$S_{11}$ (dB)	–	-15	–	–	-16	–	–	-17	–	–	-17	–
$S_{22}$ (dB)	–	-6.1	–	–	-6.3	–	–	-6.4	–	–	-6.8	–

Table 4. TABLE IV: Spec-violation percentages (traditional LNAs).

	$I_{NOM}$ (mA)
Violation	0.4	0.5	0.6	0.7
dB	22%	23%	16%	16%
$G>11$ dB	11%	10%	11%	7%
NF $>3$ dB	0%	0%	0%	0%
IIP3  dBm	14%	8%	1%	0% (1/1000)
$S_{11}>-10$ dB	0%	0%	0%	0%
$S_{22}>-10$ dB	3%	3%	2%	2%

Table 5. TABLE V: Receiver-level compliance based on traditional LNAs.

	$I_{NOM}$ (mA)
Outcome	0.4	0.5	0.6	0.7
Meet both specs	77%	79%	86%	86%
NF out of spec	21%	21%	14%	14%
IIP3 out of spec	6%	0% (3/1000)	0%	0%

Table 6. TABLE VI: Dimensions of the programmable LNA (PLNA).

Parameter	MG-LP / HG,LG
$I_{DD}$ (mA)	0.43 / 0.56
$W_1/L_1$ ($\mu$m/$\mu$m)	42/0.12
$W_3/L_3$ ($\mu$m/$\mu$m)	14/0.12
$L_s$ (nH)	2.38
$L_g$ (nH)	11.23
$C_X$ (fF)	246
$C_1$ (fF)	426
$C_P$ (pF)	1.59
$L_D$ (nH)	10.5

Table 7. TABLE VII: Mean and worst-case values from Monte Carlo (PLNA modes).

	HG			MG-LP			LG
Parameter	min	mean	max	min	mean	max	min	mean	max
$G$ (dB)	10.1	11.9	13.1	8.48	10.5	11.9	7.58	9.5	10.8
NF (dB)	–	2.5	–	–	2.9	–	–	3.6	–
IIP3 (dBm)	-8.9	2.3	–	-11.0	-1.5	–	-9.2	2.4	–
$S_{11}$ (dB)	–	-14	–	–	-16	–	–	-14	–
$S_{22}$ (dB)	–	-8.3	–	–	-8.1	–	–	-8.2	–

Table 8. TABLE VIII: Mean and worst-case values after PLNA mode selection.

Parameter	Best Gain			Best Receiver
	min	mean	max	min	mean	max
G (dB)	9.73	10.5	11.3	9.97	10.7	11.8
NF (dB)		2.4	2.99		2.3	2.98
IIP3 (dBm)	-9.0	-0.7		-8.9	-0.9
S11 (dB)		-23	-14		-24	-14
S22 (dB)		-19	-8.1		-19	-8.1

Table 9. TABLE IX: Receiver-level compliance after PLNA mode selection.

Outcome	Best Gain	Best Receiver
Meet both specs	85%	92%
NF out of spec	7%	0%
IIP3 out of spec	9%	8%

Equations

$$F_{\mathrm{Rx}}$$

$$\frac{1}{{IIP3}_{\mathrm{Rx}}}$$

$$F_2$$

$$F_{\mathrm{Rx}}$$

$$\frac{I_{D1}}{W_1}=\frac{I_{D1}+I_{D3}}{W_1+W_3},$$

Full text

I Introduction

Short-range wireless communication devices are continually expanding their application scope, which poses several design challenges, including miniaturization, low-voltage operation, and low power consumption. Data transfer in these applications also requires receivers with a wide dynamic range due to the variability of signal levels in the radio-frequency (RF) channel and the presence of high interference [1]. Fulfilling these demands introduces several design trade-offs in the implementation of the different blocks of the RF front-end [2], primarily in the low-noise amplifier (LNA), the first active block of the receiver.

The LNA determines the receiver’s sensitivity through sufficiently high gain and a low noise figure [2, 3]. However, excessive gain may saturate subsequent blocks (e.g., the mixer) under high input levels, posing a design trade-off. At the same time, the LNA must provide good input impedance matching, sufficiently high linearity, and enough reverse isolation.

The common-source LNA with inductive source degeneration (Fig. 1) is a widely used topology in integrated CMOS receivers for short-range communication systems [3, 4, 5]. Design methodologies for this topology are typically focused on noise figure and power minimization [6, 7, 8]. Moreover, the design flow must account for the effects of process variations, given their significant impact in deep-submicron CMOS technologies [9, 10]. Several works have analyzed the impact of process variations on this topology and ways to mitigate their consequences [11, 12, 13, 14, 15, 16]. Nevertheless, those studies focus on specific LNA parameters without analyzing their relationships to receiver-level performance, nor the influence of power consumption on the effects of process variations.

In this work, we employ an architecture with digitally controllable gain and power consumption proposed in [17] to mitigate process-variation effects in a $130\text{\,}\mathrm{n}\mathrm{m}$, $1.2\text{\,}\mathrm{V}$ CMOS LNA. The design is grounded on Monte Carlo simulations that analyze parameter variability in the traditional LNA and its influence on receiver performance across different bias current levels. Two adjustment strategies are evaluated: (i) a method based on measuring the deviation of gain with respect to its nominal value and (ii) a method based on receiver-level performance parameters. Results show that the proposed architecture reduces the number of receiver failures caused by process variations in the LNA while preserving low power consumption compared to the conventional architecture.

II Analysis and Design of Traditional LNAs

II-A Topology

Figure 1 shows the basic schematic of a common-source (CS) LNA with inductive degeneration. Inductive degeneration (through $L_{s}$) produces a resistive component in the input impedance without introducing an extra noise source [18]. Capacitor $C_{X}$ helps minimize the noise figure (NF) for specific gain and power levels [19]. The gate inductor $L_{g}$ is included to tune the input impedance. Transistor $M_{2}$ is used as a cascode stage to reduce the Miller effect on $M_{1}$ and improve reverse isolation [3]. The drain inductor $L_{D}$ forms a parallel resonant network together with the output capacitances of the cascode and the load impedance. Finally, the capacitive divider ($C_{1}$, $C_{P}$) is included to match the output impedance to $50\text{\,}\mathrm{\SIUnitSymbolOhm}$ for characterization of the standalone LNA with a spectrum analyzer.

In the design of a CS-LNA for a given gain and power, the transistors can be sized to minimize the noise figure, as shown in prior work for this topology [6, 7, 19]. High input-referred third-order intercept point (IIP3) at low power can be achieved by biasing MOS transistors in moderate inversion to exploit the linearity sweet spot [20]. This IIP3 peak occurs approximately at the same current density in the common-source device [21, 22]. Therefore, for a given power budget, linearity can also be maximized by adjusting the device size appropriately.

Based on this topology, we designed several LNAs with different bias currents. Then we studied the effects of process variations on their parameters and the expected impact on overall receiver performance.

II-B Design Space Exploration

The LNAs were sized by exploring the design space in the available technology, targeting the RF specifications in Table I for a ZigBee/IEEE 802.15.4 receiver [23, 24]. Input and output reflection coefficients ($S_{11}$ and $S_{22}$) are referred to $50\text{\,}\mathrm{\SIUnitSymbolOhm}$.

We swept the bias current $I_{D}$ and the width of the transistor $M_{1}$ ($W_{1}$). The width of $M_{2}$ was set to $W_{2}=W_{1}/2$ to reduce its contribution to load capacitance and enlarge the selection margin for the output matching network [4]. The channel length of all transistors was fixed to the minimum value allowed by the technology, $L_{1}=L_{2}=L=$0.12\text{,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$$. For each combination of current and transistor widths, the passive components were chosen to meet the gain and matching requirements.

Figure 2 shows simulated results at $2.45\text{\,}\mathrm{G}\mathrm{H}\mathrm{z}$ for NF and IIP3. All the shown designs meet $S_{11},S_{22}<-15$ dB and gain in $[10.3,10.9]$ dB. Minimum values of $W_{1}$ for $I_{D}=$0.4\text{,}\mathrm{m}\mathrm{A} ($24\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$) and $I_{D}=$0.3\text{\,}\mathrm{m}\mathrm{A} ($32\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$) were limited by the practical values of the passive elements in the technology while still satisfying gain and matching. All synthesized LNAs met the NF specification (NF $<3$ dB). However, the linearity requirement (IIP3 $>-4$ dBm) is not met for $I_{D}=$0.3\text{,}\mathrm{m}\mathrm{A}$$, which is therefore discarded as a bias option, and no lower currents were consequently analyzed.

As case studies, we selected amplifiers with $I_{D}\in\{0.4,0.5,0.6,0.7\}$ mA. For each power level, we chose the LNA with the highest IIP3. The resulting sizing is listed in Table II. A simple current mirror was used as the biasing circuit.

II-C Variability Analysis

For each selected LNA, we performed a Monte Carlo simulation with 1000 runs, incorporating both process and mismatch variations, as specified by the PDK’s statistical distributions. Table III summarizes mean and worst-case values of the simulated parameters, while Table IV lists the percentage of specification violations.

From Table III, the mean IIP3 increases as bias current goes from $0.4\text{\,}\mathrm{m}\mathrm{A}$ to $0.6\text{\,}\mathrm{m}\mathrm{A}$. The mean values of the remaining parameters vary little across designs. In worst-case terms, IIP3 exhibits the largest improvement as the current increases. Input matching ($S_{11}$) and noise figure specifications are met in all cases, whereas output matching ($S_{22}$) shows a low probability of violation ($<3\%$). The number of IIP3 violations drops from 14% to just 1% when increasing the current from $0.4\text{\,}\mathrm{m}\mathrm{A}$ to $0.6\text{\,}\mathrm{m}\mathrm{A}$.

By contrast, gain is the parameter with the highest probability of falling outside the specification, most often due to $G<10$ dB. This is significant because gain variations affect both receiver noise and linearity, even when NF and IIP3 of the LNA itself meet their limits.

The implications at receiver level can be studied using the cascade equations that relate LNA parameters ($F_{\mathrm{LNA}}$, $\mathrm{IIP3}_{\mathrm{LNA}}$) to receiver parameters ($F_{\mathrm{Rx}}$, $\mathrm{IIP3}_{\mathrm{Rx}}$) and to the subsequent stages ($F_{2}$, $\mathrm{IIP3}_{2}$) [2]:

[TABLE]

where $F$ denotes the noise factor ($F=10^{\mathrm{NF}/10}$) and $G_{\mathrm{LNA}}$ is the linear power gain.

Using the LNA specs of Table I and receiver targets ($\mathrm{NF}_{\mathrm{Rx}}\leq$15.5\text{,}\mathrm{d}\mathrm{B} and $\mathrm{IIP3}_{\mathrm{Rx}}\geq$-10\text{\,}\mathrm{d}\mathrm{B}\mathrm{m}) [23], the limits for the remainder of the chain can be computed:

[TABLE]

Assuming receivers that include the simulated LNAs and subsequent stages sized at these limits, such receivers meet the specs if

[TABLE]

Table V summarizes the percentage of receivers that simultaneously meet both noise and linearity specs and those failing noise or linearity, respectively.

The LNA parameter variations affect receiver noise more than linearity. When $G$ drops below its minimum, the LNA cannot suppress the noise of the following stages even if $F_{\mathrm{LNA}}$ itself is small. In contrast, receiver linearity is less sensitive to the LNA since this is the stage with the lowest input signal level; thus, maintaining a high $\mathrm{IIP3}_{\mathrm{LNA}}$ prevents most linearity failures even when gain increases.

One possible solution to compensate for gain loss—and thus increase the number of compliant cases—would be to improve the noise figure of the subsequent stages, primarily the mixer. However, this would complicate implementation because system-level specifications would need to be redistributed, and some blocks would require redesign. Moreover, reducing the noise figure typically requires higher power consumption in the corresponding block [25]. To avoid these drawbacks, we evaluate an LNA architecture with controllable gain and power to mitigate process-variation effects at the LNA itself.

III Using a Programmable Architecture to Mitigate LNA Performance Degradation

The programmable LNA (PLNA) architecture proposed in [17] and shown in Fig. 3 extends the traditional CS-LNA. An extra parallel branch is added, comprised of a transconductor ($M_{3}$) and a cascode pair that acts as a current switch ($M_{4}$ to the output network, $M_{5}$ to $V_{DD}$). This branch combines two control techniques: gain control via a current-splitting variant [26] and power control via transistor width scaling [27]. The topology supports several digitally selected operating modes through the control inputs $\Phi$ and $\Phi_{g}$, providing both gain and power control.

Complementary switching $M_{4}$ and $M_{5}$ ($\Phi=1/0$, $\Phi_{g}=0/1$) either delivers the RF current flowing through $M_{3}$ to the load (high-gain mode, HG) or diverts it to ground via $V_{DD}$ (low-gain mode, LG). Because the operating point of $M_{3}$ remains constant during switching, the input impedance is unaffected.

When both $M_{4}$ and $M_{5}$ are off ($\Phi=\Phi_{g}=0$), current through $M_{3}$ ceases, which reduces power but also changes the input impedance. In this mode, the RF signal at the output flows only through $M_{2}$, as in LG. However, the change in input impedance makes the gain values differ; we observed that the lowest-power mode provides an intermediate gain. Therefore, the combination $\Phi=\Phi_{g}=0$ yields a medium-gain, low-power mode (MG-LP).

In the implemented power scaling, with fixed gate bias for the common-source devices, the equivalent current density is kept constant,

[TABLE]

which allows all modes to operate around the current-density region where the IIP3 peak appears. From the higher-current modes, one also expects more stable linearity under process variations, consistent with the traditional-LNA results.

The ratio $W_{1}/W_{3}$ determines both the achievable gain steps and the change in bias current. This ratio is limited by the permissible degradation in input matching, which sets a design tradeoff for the PLNA [28].

III-A Design

We set the medium gain equal to the previous target of $10.5\text{\,}\mathrm{d}\mathrm{B}$. Simulations showed that a $3{:}1$ ratio between $W_{1}$ and $W_{3}$ provides $+1.5$ dB and $-1.0$ dB gain steps around the medium-gain value while maintaining acceptable input matching across modes. Hence, a worst-case $-2$ dB gain drop (i.e., $8.5\text{\,}\mathrm{d}\mathrm{B}$ in MG-LP, similar to the worst cases in Table III) can be reduced to a $-0.5$ dB deviation by switching to HG. Likewise, LG can recover worst-case scenarios with a $+1.5$ dB excess gain back to within specification.

With this aspect ratio, $M_{1}$ and $M_{3}$ were dimensioned and biased near the IIP3 sweet spot (Fig. 2) while minimizing power. We selected $\{W_{1};I_{D1}\}=\{3W_{3};3I_{D3}\}=\{$42\text{,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$;$0.4\text{,}\mathrm{m}\mathrm{A}$\}$ for MG-LP, which yields the equivalent operating point $\{W_{1}+W_{3};I_{D1}+I_{D3}\}=\{4W_{3};4I_{D3}\}=\{$56\text{,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$;$0.53\text{,}\mathrm{m}\mathrm{A}$\}$ for the higher-power modes (HG and LG). The final dimensions are listed in Table VI. The value of $L_{D}$ is the same as in Table II. $I_{DD}$ includes the current delivered to the bias circuitry.

The passive components of the PLNA differ only slightly from those of the $0.4\text{\,}\mathrm{m}\mathrm{A}$ traditional LNA ($<5\%$ in inductors and $<7\%$ in capacitors). Therefore, the occupied die area (mainly determined by the inductor sizes) is expected to be practically unaffected by the programmable architecture.

III-B Variability Analysis

We ran 1000-run Monte Carlo simulations for each PLNA mode. Table VII lists mean and worst-case values.

Comparing MG-LP to the $0.4\text{\,}\mathrm{m}\mathrm{A}$ traditional LNA, only IIP3 shows a lower mean value, yet it still meets the spec. Worst-case behavior is similar in both amplifiers. Therefore, introducing programmability does not practically degrade the base amplifier performance. In the higher-power modes, IIP3 improves while input matching degrades (yet remains within limits). The minimum and maximum gains in HG and LG, respectively, also comply with the required range.

IV PLNA Results With Mode Selection Under Process Variations

From the Monte Carlo results, for each sample, we selected the operating mode according to two criteria:

• •

Best Gain: choose the mode with the smallest deviation of LNA gain from $10.5\text{\,}\mathrm{d}\mathrm{B}$.

• •

Best Receiver: choose the mode for which the receiver meets both NF and linearity limits in (1)–(2). If this is not possible, select a mode that at least meets the NF condition; if none is possible, choose the mode with the largest dynamic range.

These two criteria were considered because both are compatible with integrated BIST solutions [29, 30, 31] that could enable automatic adjustment.

Table VIII shows mean and worst-case RF parameters after mode selection for each criterion, and Table IX summarizes receiver-level compliance and failures.

Both selection methods yield very similar worst-case scenarios, except for gain, which is higher when prioritizing receiver compliance because this criterion favors NF improvement; as a side effect, the maximum gain increases. As expected, the receiver-based selection increases the fraction of fully compliant receivers. With this method, we fully compensated all cases where gain loss caused the receiver NF to fail. The two methods show approximately the same number of cases where linearity could not be compensated. Selecting one method or the other will also depend on the practical pros and cons of the corresponding BIST implementations.

IV-A Performance Comparison With Traditional LNAs

Compared to the traditional LNAs, the PLNA with either selection method shows clear improvements. In worst-case terms, only NF and $S_{11}$ degrade after adjustment. NF degradation occurs due to the LG mode [32], while $S_{11}$ degradation stems from operating-point changes; yet all cases remain within limits.

Figure 4 compares the PLNA performance after adjustment (both selection methods) with the traditional LNAs in terms of the difference in the number of compliant cases ($\Delta S$) and the average power consumption difference ($\Delta P$), each normalized to the total number of cases and to the power of each LNA, respectively. The “Best Gain” method reaches practically the same compliance rate as the $0.6\text{\,}\mathrm{m}\mathrm{A}$ and $0.7\text{\,}\mathrm{m}\mathrm{A}$ LNAs (differences $<1\%$) with 26% and 35% lower average power, respectively. It also improves the compliance rate of the $0.4\text{\,}\mathrm{m}\mathrm{A}$ LNA by 8% at the cost of only 9% more power—a balanced tradeoff. The “Best Receiver” method exceeds the compliance rate of all analyzed traditional LNAs with average power only higher than that of the $0.4\text{\,}\mathrm{m}\mathrm{A}$ design; relative to that design, it consumes merely 5% more power while delivering a 15% improvement in compliance.

V Conclusions

We presented a digitally controllable-gain, power-scalable LNA architecture to mitigate process-variation effects in a $130\text{\,}\mathrm{n}\mathrm{m}$, $1.2\text{\,}\mathrm{V}$ CMOS technology. By adjusting transistor operating points through digital inputs as a function of RF parameter degradation, the architecture reduces the number of receiver failures caused by LNA variability while maintaining low power consumption compared to traditional LNA designs.

Two different adjustment strategies were evaluated: one based on gain deviation and another based on receiver performance, both of which outperformed the traditional LNA. The second method shows a better balance between the number of compliant receivers and average power consumption.

The proposed architecture requires adding only a few devices (transistors) to the standard common-source, inductively degenerated LNA topology. Passive components change only slightly compared to the reference traditional LNA, so the die area should not increase significantly. The presented methodology — leveraging prior designs of the traditional LNA and requiring only minor changes — also allows for implementing the solution without a significant increase in design time and effort.

Acknowledgment

This work was supported by CAPES (Brazil), Project 176/12; CNPq; MAEC-AECID through project FORTIN (Ref. D/024124/09); FEDER program of the Junta de Andalucía, project P09-TIC-5386; and the Spanish Ministry of Economy and Competitiveness, project TEC2011-28302. The authors thank Prof. Agnes Nagy (CIME-CUJAE) for her valuable comments.