# A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs (English Version)

## TL;DR

This paper introduces a digitally controllable CMOS LNA architecture that adjusts gain and power to improve yield and performance amidst process variations, maintaining low power consumption.

## Contribution

It proposes a novel architecture for CMOS LNAs with digital control for gain and power, enhancing yield and robustness against process variations.

## Key findings

- Achieved yield improvement with the proposed architecture.
- Maintained low-power operation comparable to traditional LNAs.
- Validated the approach with a 130 nm CMOS LNA design.

## Abstract

This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI{130}{nm}, \SI{1.2}{V} LNA implementing the proposed architecture is designed based on an analysis of variability in traditional LNAs under different bias currents and on the corresponding effects on the performance of a complete receiver. Two different adjustment strategies are evaluated, both of which are compatible with previously reported built-in self-test (BIST) circuits. Results show that the proposed architecture enables yield enhancement while keeping low-power operation compared with traditional LNAs.