MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

TL;DR

The paper introduces MUX64, an analogue multiplexer ASIC designed for the ATLAS HGTD, demonstrating reliable performance and minimal degradation after accelerated aging tests.

Contribution

This work presents the design, fabrication, and testing of a novel 64-to-1 analogue multiplexer ASIC for high-energy physics detectors.

Findings

Successful fabrication of 280 ASIC chips.

Negligible performance degradation after 16 days at 85°C.

Reliable selection and transmission of 64 analog signals.

Abstract

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days.

Full text

1 Introduction

The High-Luminosity Large Hadron Collider (HL-LHC) at CERN aims for delivering an integrated luminosity up to 4000 $\mathrm{f}\mathrm{b}^{-1}$. The instantaneous luminosity will be increased to $7.5\times 10^{34}\,\mathrm{c}\mathrm{m}^{-2}\mathrm{s}^{-1}$, which is a factor 3-4 to the Run2 of the LHC. The event pileup caused by higher luminosity is one of the main challenges at the HL-LHC. The High Granularity Timing Detector (HGTD) [1] of the ATLAS Phase-@slowromancapii@ upgrade [2] is in construction to mitigate the pileup effects.

The HGTD detector module consists of a Low-Gain Avalanche Detectors (LGAD) [3] sensor bump-bonded to two readout chips (ALTIROC [4]) for a timing resolution of $25\,\mathrm{p}\mathrm{s}$. In the peripheral area surrounding the detector modules, the Peripheral Electronics Boards (PEBs) transmit the data between the front-end detector modules and the data acquisition (DAQ) system, the detector control system (DCS) and the luminosity systems. The detector modules are connected to the PEBs via flexible circuit cables (FLEX) [5]. It is important to monitor the temperatures of the LGAD sensors and the supply voltage drops in FLEX cables. The analogue signals being monitored are read by the ADC of the Low Power Giga Bit Transceiver (lpGBT [6]) mounted on the PEBs.

To accommodate the large number of monitored channels for the detector modules, the design incorporating a multiplexer is necessary for readout by a single ADC channel on an lpGBT. The MUX64, a 64-to-1 analogue multiplexer has been developed to meet the requirements. Six GPIO output ports of the lpGBT are connected to the MUX64 to select an input signal transferred to the output. Compared to commercial multiplexers, the MUX64 handles more (up to 64) inputs. The total of 1300 MUX64 chips will be produced for the HGTD, which include 15% spare.

This paper is organized as the following: in section 2 we describe the monitoring system for the detector modules of the HGTD. The design of MUX64 and the requirements are discussed in Section 3. The prototype MUX64 chips were examined and the results are presented in section 4. A summary and outlook on radiation test are discussed in 5.

2 Monitoring of the HGTD detector modules

The digital and analogue supply voltages on the HGTD detector modules and the DC/DC regulators shall be monitored for operating stability and the supply voltage drops passing through the FLEX cable. Detecting voltage change at the module level is an effective method for finding possible latch-up events on an ALTIROC. The LGAD sensors which are sensitive to temperature will be operated at $-30\,\degreecelsius$ to reduce leakage current. The temperature sensors are implemented inside the ALTIROC chips which provide a resolution of $0.2\,\degreecelsius$ to detect loss of cooling and thermal runaway in a range from $-40$ to $+40\,\degreecelsius$.

Figure 1 shows the schematic of the monitoring of a detector module. A total of 6 signals are sent to the MUX64. Three of them are the supply voltages and analogue grounding ($\mathrm{V}_{\mathrm{ddd\_probe}}$, $\mathrm{V}_{\mathrm{dda\_probe}}$ and $\mathrm{V}_{\mathrm{Gnda\_probe}}$), another two are the analogue signals from 2 ALTIROC ($\mathrm{ASIC_{probe0}}$, $\mathrm{ASIC_{probe1}}$), and one from thermistor (NTC). These signals are stable low-frequency analogue signals. The expected switching frequency in the monitoring system is about $100\,\mathrm{Hz}$. This is below the MUX64 specification of $1\,\mathrm{k}\mathrm{Hz}$. Up to 10 detector modules can be monitored by a MUX64 to an ADC channel of a single lpGBT.

3 MUX64 Chip design

3.1 Specifications

The MUX64 is designed for processing 64 analogue inputs to one output. The operating temperature range is $-35\,\degreecelsius$ to $+40\,\degreecelsius$. The power consumption of a MUX64 should be smaller than $1\,\mathrm{m}\mathrm{W}$. The input dynamic range is $0.0$ to $1.0\mathrm{V}$, and the output is read by the 10-bit ADC of the lpGBT.

The input impedance of the ADC is evaluated to be about $4.8\,\mathrm{M}\mathrm{\SIUnitSymbolOhm}$. $R_{\mathrm{ON}}$ of the MUX64 is the resistance between selected "ON" input channels and the output, which is recommended to be lower than $900\,\mathrm{\SIUnitSymbolOhm}$ for matching the precision of the ADC. The $R_{\mathrm{OFF}}$ between the "OFF" channels and the output is required to be larger than $60\,\mathrm{M}\mathrm{\SIUnitSymbolOhm}$. Due to the limited space on PEBs, the MUX64s are packaged in the miniature QFN88 format with a size of $1\,\mathrm{c}\mathrm{m}\times 1\,\mathrm{c}\mathrm{m}$.

The MUX64 on the HGTD PEBs will be located at a radial distance near $700\,\mathrm{m}\mathrm{m}$ from the beam pipe center. Radiation tolerance is one of the most important requirements. For the HL-LHC operation period, the MUX64 shall be able to withstand a total ionizing dose (TID) of $0.5\,\mathrm{M}\mathrm{Gy}$ and the $1\,\mathrm{M}\mathrm{eV}$ equivalent neutron fluence of $1.5\times 10^{15}\,(\mathrm{Si})\,n_{\mathrm{eq}}/\mathrm{c}\mathrm{m}^{2}$.

3.2 MUX64 schematic and logic

The block diagram of the MUX64 is shown in Figure 2a. The MUX64 uses transmission gates as analogue switches to transmit only one of the 64 input signals to the output. In the transmission gate circuit, the dimension of PMOS is $\mathrm{L}=130\,\mathrm{n}\mathrm{m},\,\mathrm{W}=10\,\mathrm{\SIUnitSymbolMicro}\mathrm{m}$ and the dimension of NMOS is $\mathrm{L}=130\,\mathrm{n}\mathrm{m},\,\mathrm{W}=8\,\mathrm{\SIUnitSymbolMicro}\mathrm{m}$. A 6-bit decoder is implemented inside the MUX64 to determine the channel to be connected to the output. The decoder controls the switches of the transmission gates.

The MUX64 is designed and manufactured using the TSMC 130nm CMOS technology. The layout with Enclosed Layout Transistors (ELTs) is employed to enhance radiation tolerance. The decoder is implemented with Triple Modular Redundancy (TMR) structure for fault tolerance against Single Event Upset caused by radiation.

4 MUX64 Chip Test

A total of $276$ dies were prepared for characteristic studies. Twelve dies were wire-bonded on test boards for performance in temperature change ranging from $-40\,\degreecelsius$ to $80\,\degreecelsius$. The others were packaged in QFN88 format which were examined for quality assurance. The MUX64 test kits are shown in figure 3. The packaged chips were tested channel by channel with the input voltage ramping from $0.0$ to $1.2\mathrm{V}$.

The schematic of the MUX64 test setup is shown in figure 4. The multiplexing functionality of the 64-to-1 is validated with an Agilent B2912A 2-channel precision source/measure unit which provides analogue voltage signals ($\mathrm{V}_{\mathrm{in}}$, A1 and $5\,\mathrm{V}$, A2 in figure 4). The MUX64 ON-channel is selected by six GPIO ports on the isolated USB programmer board for lpGBT (UPL) [7]. The input signals are connected to MUX64 via electromagnetic relays. A total of 64 relays are controlled by a computer interface in the test. The output signal is measured by an Agilent 34410A digital multimeter (V) on a $10\,\mathrm{k}\mathrm{\SIUnitSymbolOhm}$ load.

The $R_{\mathrm{ON}}$ of a wire-bonded MUX64 channel is tested and plotted in figure 6. The input voltage varies from $0.05\,\mathrm{V}$ to $1.20\,\mathrm{V}$ in steps of $0.05\,\mathrm{V}$ at chosen temperatures ranged from $-41\,\degreecelsius$ to $+85\,\degreecelsius$. The maximum $R_{\mathrm{ON}}$ is measured at $0.65\,\mathrm{V}$, which increases as the temperature decreases. At $-31\,\degreecelsius$ the $R_{\mathrm{ON}}$ peak is about $900\,\mathrm{\SIUnitSymbolOhm}$ which meets the design criteria. The rise of $R_{\mathrm{ON}}$ at $0.65\,\mathrm{V}$ is caused by the transmission gate switch consisting of a PMOS and an NMOS transistor, as is plotted in figure 2b. The PMOS affects the $R_{\mathrm{ON}}$ to increase nonlinearly with the input voltage while the NOMS does the opposite. The combined effects result in the distributions are shown in figure 6 and 6.

All the test samples were examined for the multiplexing function of every channel at room temperature. In figure 6 the $R_{\mathrm{ON}}$ of all 64 channels tested are plotted for a QFN88 packaged  MUX64. The OFF channel resistance is specified for $60\,\mathrm{M}\Omega$. With all 64 channels turn off, the leakage to output is measured to be $25\,\mathrm{n}\mathrm{A}$. The individual $R_{\mathrm{off}}$ is sufficiently larger than the specified.

The power consumption of the MUX64 is examined for temperature dependence. In figure 7a, the current of a MUX64 with a channel turned on is plotted versus temperature. The MUX64 power consumption decreases with operating temperature. At the detector operating temperature of $-30\,\degreecelsius$, the power consumption at $1.2\,\mathrm{V}$ is $\sim 0.1\,\mathrm{\SIUnitSymbolMicro}\mathrm{W}$. The uniformity of channels in operation is examined for the current variation, as is plotted in figure 7b. The current of MUX64 is measured at $18\,\degreecelsius$ with the channels switched ON in sequence. The average current measured is $0.93\pm 0.06\,\mathrm{\SIUnitSymbolMicro}\mathrm{A}$. The variance is less than 7%.

The reliability of MUX64 was further tested in burn-in. In the setup shown in figure 8a, a total of 32 QFN88 packaged MUX64 chips were mounted on a Batch-Test (BT) board. The BT board has 64 signals at different voltages each connected by fan-out cables to all the MUX64s in the test. In the burn-in conducted at $85\,\degreecelsius$, all the test samples withstood well over 16 days. Figure 8b shows the $R_{\mathrm{ON}}$ deviation in 64 channels with different input voltages of a MUX64 monitored during the burn-in. The maximum deviations on $R_{\mathrm{ON}}$ of all the MUX64s in all channels are smaller than $5\,\mathrm{\SIUnitSymbolOhm}$, which demonstrates the stability required for inputs to the ADC of the lpGBT.

5 Conclusions and outlook

We present the design and performance of MUX64. The prototype samples were tested and the result met design requirements. The burn-in test at 85 $\degreecelsius$ with 32 chips shows negligible degradation over 16 days. Quality assurance will be conducted on all the QFN packaged MUX64s with thermal cycles and channel-by-channel tests.

The radiation tolerance of MUX64 is required. Irradiation test was carried out with the CSNS  [8] $80\,\mathrm{M}\mathrm{eV}$ proton beam. The test samples had withstood a fluence of $2.10\times 10^{15}\,(\mathrm{Si})\,n_{\mathrm{eq}}/\mathrm{c}\mathrm{m}^{2}$, which meets the requirement for HGTD. The tolerance with total ionizing doze (TID) is in progress using an X-ray irradiation facility.

Acknowledgments

We sincerely thank the Omega group (Omega/Ecole Polytechnique/CNRS, France) for their helpful assistance in the fabrication of the MUX64. This work is supported in part by the National Natural Science Foundation of China (NSFC) under the Contract $\mathrm{No.}\,12122507$. This work is supported by the National Natural Science Foundation of China ($\mathrm{No.}\,11961141014$)