Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips

TL;DR

This paper introduces DS3, a fast, system-level simulation framework for domain-specific SoCs that enables efficient design exploration and resource management, significantly outperforming traditional simulators like gem5.

Contribution

The paper presents a novel simulation framework, DS3, optimized for domain-specific SoCs, providing rapid, accurate system-level evaluations for power and performance.

Findings

DS3 achieves ~600x speedup over gem5.

DS3 effectively supports design exploration and dynamic resource management.

Open-source release of DS3 and applications to foster research.

Abstract

Heterogeneous system-on-chips (SoCs) have become the standard embedded computing platforms due to their potential to deliver superior performance and energy efficiency compared to homogeneous architectures. They can be particularly suited to target a specific domain of applications. However, this potential is contingent upon optimizing the SoC for the target domain and utilizing its resources effectively at run-time. Cycle-accurate instruction set simulators are not suitable for this optimization, since meaningful temperature and power consumption evaluations require simulating seconds, if not minutes, of workloads. This paper presents a system-level domain-specific SoC simulation (DS3) framework to address this need. DS3 enables both design space exploration and dynamic resource management for power-performance optimization for domain applications with$~600\times$ speedup compared to commonly used gem5 simulator. We showcase DS3 using five applications from wireless communications and radar processing domain. DS3, as well as the reference applications, will be shared as open-source software to stimulate research in this area.

Tables

Table 1. Table 1. Execution profiles of WiFi-TX on Arm A7/A15 cores in Odroid-XU3 and hardware accelerators

Sample App.	Task	Latency ($\mu$s)
		HW Acc.	Odroid A7	Odroid A15
WiFi-TX	Scrambler Enc.	8	22	10
	Interleaver		10	4
	QPSK Modulation		15	8
	Pilot Insertion		5	3
	Inverse-FFT	16	296	118
	CRC		5	3

Table 2. Table 2. SoC configuration for scheduling case studies

Resource	Type	# of Instances
Cortex-A15	ARM big Architecture	4
Cortex-A7	ARM LITTLE Architecture	4
Scrambler-Encoder	Hardware Accelerator	2
FFT	Hardware Accelerator	4

Full text

Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips

Samet E. Arda1, Anish NK1, A. Alper Goksoy1, Joshua Mack2, Nirmal Kumbhare2,

Anderson L. Sartor3, Ali Akoglu2, Radu Marculescu3 and Umit Y. Ogras1

1School of Electrical Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

2Electrical and Computer Engineering, The University of Arizona, Tucson, AZ, USA

3Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA

(2019) ††copyright: acmcopyright††journalyear: 2019††conference: International Conference on Hardware/Software Codesign and System Synthesis; October 13–18, 2019; New York, NY, USA††booktitle: International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS ’19), October 13–18, 2019, New York, NY, USA††price: 15.00††doi: 10.1145/3349567.3351719††isbn: 978-1-4503-6923-7/19/10

1. Introduction and Background

Homogeneous general purpose processors provide flexibility to implement a variety of applications and facilitate programmability. In contrast, heterogeneous system-on-chips (SoCs) that combine general purpose and specialized processors offer great potential to achieve higher efficiency while maintaining programming flexibility. In particular, domain-specific SoCs (DSSoC), a class of heterogeneous architectures, tailor the architecture and processing elements (PE) to a specific domain. Hence, they can provide superior energy-efficiency compared to general purpose processors by exploiting the characteristics of target applications.

DSSoCs can fulfill their potential only if they integrate the set of accelerators required by the target domain and utilize these resources effectively. Therefore, the first step in the design of DSSoCs is analyzing the domain applications to identify the most commonly used kernels. This analysis is necessary to determine the set of hardware accelerators in the architecture. For example, a DSSoC that targets wireless communications domain will most likely have Fourier transform (FFT) accelerators. The next step is to design the DSSoC, including the PEs and network-on-chip that interconnects them. Then, a wide range of design- and run-time algorithms are employed to schedule the domain applications to the PEs in the DSSoC (smit2005run, ; de2010dynamic, ). Similarly, dynamic voltage and frequency scaling (DVFS) policies, such as Ondemand and thermal management techniques have been applied to efficiently manage the power and temperature of SoCs (bhat2018algorithmic, ). However, existing approaches are typically evaluated in isolated environments and different in-house tools. Thus, there is a strong need for a unified simulation environment to enable design space exploration and dynamic resource management of domain applications.

StarPU framework provides the ability to perform run-time scheduling and execution management for directed acyclic graph (DAG) based programs on heterogeneous architectures (augonnet2011starpu, ). It is integrated into SimGrid (casanova2013simgrid, ) framework. However, SimGrid was developed in the context of providing fast simulation for distributed systems, and the authors acknowledge that it is not intended to scale down to simulating real-time multi-threaded systems or comparing kernel schedulers and policies (simgrid-limits, ). A recent work (xiao2019self-optimizing, ) targets domain-specific programmability of heterogeneous architectures through intelligent compile- and run-time mapping of tasks across different PEs. In this study, the authors employ three different simulators. The proposed framework would benefit this and other similar studies by providing a single integrated simulation framework.

In this work, we present an integrated open-source simulation framework capable of evaluating both scheduling and dynamic thermal-power management algorithms. It addresses rapid system-level power, performance, and temperature exploration of DSSoCs. Besides facilitating the design of new scheduling and dynamic thermal-power management (DTPM) algorithms, the proposed framework also features built-in DVFS governors deployed on commercial SoCs and analytical power, performance, and temperature models. Finally, the framework includes five reference applications from wireless communication and radar processing domains. These applications are profiled on commercial heterogeneous SoC platforms and provided as a benchmark suite integrated to our framework.

2. Overview

The goal of the proposed simulation framework is to enable rapid development of scheduling and power management algorithms while enabling extensive DSSoC design space exploration.

The organization of the framework, designed to accomplish these objectives, is shown in Figure  1. The resource database contains the list of PEs along with expected latency of tasks in the application(s). The simulation is driven by the job generator which injects instances of an applications to the simulator following a given probability distribution. As an example, Figure  2 presents a block diagram for a WiFi transmitter (WiFi-TX) job that is composed of multiple tasks. The dependency among the tasks is represented using a DAG. Hence, the job generator produces the tasks for a transmitter job along with their dependencies.

The simulation framework invokes the scheduler at every scheduling decision epoch with the list of tasks ready for execution. Then, the simulation kernel simulates task execution on the corresponding PE using execution time profiles obtained from our reference hardware implementations. Similarly, the framework employs analytical latency models to estimate interconnect delays on the SoC. After each scheduling decision, the simulation kernel updates the state of the simulation, which is used in subsequent decision epochs.

There are three built-in scheduling algorithms: 1) Minimum execution time (MET) scheduler (heuristic_comparison, ), 2) Earliest task first (ETF) scheduler (workflow_schedule, ), and 3) A table-based scheduler which can store any offline schedule, such as an assignment generated by an integer linear programming (ILP) solver, in the form of a look-up table. In addition, the framework enables a plug-and-play interface to choose between different scheduling algorithms. Hence, developers can implement their own algorithms and integrate them easily.

In parallel, power and energy estimates of each schedule are calculated by using power models (bhat2018algorithmic, ). Using these models, the proposed framework aids the design space exploration of DTPM techniques. Similarly, the memory access and on-chip interconnect latency are modeled by the proposed framework. Finally, the framework generates plots and reports of schedule, performance, throughput, and energy consumption to aid users in analyzing the behaviour of various algorithms.

3. Scheduling Case Study

The proposed simulation framework enables evaluation of various scheduling algorithms for real-world applications with different DSSoC configurations. To this end, we developed reference designs for WiFi transmitter and receiver (WiFi-RX), low-power single-carrier, range detection, and pulse Doppler applications on two popular commercial heterogeneous SoC platforms, i.e., Xilinx Zynq ZCU-102 UltraScale MPSoC and Odroid-XU3. We profiled the task execution times for each application executed on these platforms. As an example, the execution times for different tasks in WiFi-TX are shown in Table 1. The SoC configuration chosen for the scheduling case studies are shown in Table 2.

In this study, the simulations run on an SoC configuration that mimics a typical heterogeneous SoC with a total of 14 general purpose cores and hardware accelerators. We schedule and execute the WiFi-TX task flow graph using the simulation framework and plot the average job execution time trend with respect to the job injection rate, as shown in Figure 3. To understand the performance of scheduling algorithms, we analyze the average execution time at varying rates of job injection.

All schedulers perform similar at low job injection rates (less than 5 job/$ms$). However, as the job injection rates increases, the schedule from MET results in higher execution time since MET uses a naive representation of the system state for scheduling decisions, by only considering PEs with best execution times. On the other hand, ILP uses a static table based schedule which is optimal for one job instance. At low injection rates (less than 5 job/$ms$), ILP provides a comparable schedule as jobs do not interleave. However, as the injection rate increases, the ILP schedule is not optimal. The performance of ETF is superior in comparison to the others (see Figure 3) since ETF utilizes the information about the communication cost between tasks and the current status of all PEs while making the scheduling decision.

To validate the proposed framework, we also implemented a subset of the scheduling algorithms on the Xilinx Zynq FPGA and then, compared the results for the applications in the benchmark suite with hardware measurements. In summary, the experiment presented in Figure 3 demonstrates one of the many capabilities of the simulation environment. It allows the end user to evaluate workload scenarios exhaustively by sweeping the configuration space to determine the most suitable scheduling algorithm for a given SoC architecture.