# Work-in-Progress: A Simulation Framework for Domain-Specific System-on-Chips

## TL;DR

This paper introduces DS3, a fast, system-level simulation framework for domain-specific SoCs that enables efficient design exploration and resource management, significantly outperforming traditional simulators like gem5.

## Contribution

The paper presents a novel simulation framework, DS3, optimized for domain-specific SoCs, providing rapid, accurate system-level evaluations for power and performance.

## Key findings

- DS3 achieves ~600x speedup over gem5.
- DS3 effectively supports design exploration and dynamic resource management.
- Open-source release of DS3 and applications to foster research.

## Abstract

Heterogeneous system-on-chips (SoCs) have become the standard embedded computing platforms due to their potential to deliver superior performance and energy efficiency compared to homogeneous architectures. They can be particularly suited to target a specific domain of applications. However, this potential is contingent upon optimizing the SoC for the target domain and utilizing its resources effectively at run-time. Cycle-accurate instruction set simulators are not suitable for this optimization, since meaningful temperature and power consumption evaluations require simulating seconds, if not minutes, of workloads. This paper presents a system-level domain-specific SoC simulation (DS3) framework to address this need. DS3 enables both design space exploration and dynamic resource management for power-performance optimization for domain applications with$~600\times$ speedup compared to commonly used gem5 simulator. We showcase DS3 using five applications from wireless communications and radar processing domain. DS3, as well as the reference applications, will be shared as open-source software to stimulate research in this area.