A 354Mb/s 0.37mm^2 151mW 32-User 256-QAM Near-MAP Soft-Input Soft-Output Massive MU-MIMO Data Detector in 28nm CMOS

TL;DR

This paper introduces a highly efficient 28nm CMOS ASIC for massive MU-MIMO systems, enabling 32-user 256-QAM detection with near-optimal performance, low power, and high throughput, suitable for real-world wireless applications.

Contribution

It presents a novel hardware implementation of a modified LAMA algorithm for massive MU-MIMO detection, achieving high throughput and energy efficiency in a compact chip.

Findings

Achieves 354Mb/s throughput at 151mW power consumption.

Improves SNR by over 11dB compared to existing detectors.

Provides 4x higher throughput per area than recent message-passing detectors.

Abstract

This paper presents a novel data detector ASIC for massive multiuser multiple-input multiple-output (MU-MIMO) wireless systems. The ASIC implements a modified version of the large-MIMO approximate message passing algorithm (LAMA), which achieves near-optimal error-rate performance (i) under realistic channel conditions and (ii) for systems with as many users as base-station (BS) antennas. The hardware architecture supports 32 users transmitting 256-QAM simultaneously and in the same time-frequency resource, and provides soft-input soft-output capabilities for iterative detection and decoding. The fabricated 28nm CMOS ASIC occupies 0.37mm^2 , achieves a throughput of 354Mb/s, consumes 151mW, and improves the SNR by more than 11dB compared to existing data detectors in systems with 32 BS antennas and 32 users for realistic channels. In addition, the ASIC achieves 4x higher throughput per area compared to a recently proposed message-passing detector.

Tables

Table 1. TABLE I: Performance summary and ASIC comparison

	This work	Tang [5]	Chen [6]	Tang [7]
Max UEs	$32$	$32$	$8$	$16$
Algorithm	LAMA	CHEMP	CHEMP	EPDa
Soft-in soft-out	yes	no	nob	no
Modulation	256-QAM	256-QAM	QPSK	256-QAM
Realistic channels	yes	no	no	yes
Technology [nm]	28	40	40	28
Supply [V]	0.9	0.9	0.9	1.0
Area [${\text{mm}}^2$]	0.37	0.58	0.076	2.0
Frequency [MHz]	400	425	500	569
Power [mW]	151	220.6	77.9	127
Throughput [Gb/s]​​​​	0.354	2.76	8	1.80
Energy${}^{\text{c}}$ [pJ/b]	426	79.9	9.74	70.56
Area Eff.${}^{\text{d}}$ [Gb/s/${\text{mm}}^2$]​​​​​	0.95	4.76	105.26	0.90
Norm. Energy${}^{\text{c,e,f}}$ [pJ/b]​​​​	426	39.16	76.33	215
Norm. Area Eff.${}^{\text{d,e,f}}$ [Gb/s/${\text{mm}}^2$]	0.95	13.87	19.18	0.21

Equations

$${\Lambda }_{u,q}^{\text{d}}=\log \left(\frac{\text{P}\left[x_{u,q}=1\mid \mathbf{y}\right]}{\text{P}\left[x_{u,q}=0\mid \mathbf{y}\right]}\right)-{\Lambda }_{u,q}^{\text{prior}},$$

$$\Theta =\frac{UQ}{t_{\text{max}}{T}_{\text{s}}+T_{\text{LLR}}}{f}_{\text{clk}}\text{[bit/s]}.$$

Full text

I Introduction

Massive MU-MIMO enables higher per-cell spectral efficiency compared to conventional, small-scale MIMO. This improvement, however, comes at a significant increase in baseband processing complexity [1]. In particular, data detection at the base-station (BS) in the massive MU-MIMO uplink is among the most critical tasks in terms of power consumption and throughput [2]. To exacerbate the situation, the complexity of optimal, maximum a-posteriori (MAP), data detection grows exponentially in the number of user equipment (UE) antennas [3], which prevents its implementation in practice.

To enable high-throughput massive MU-MIMO data detection, a variety of low-complexity algorithms (see, e.g., [1, 4]) and application-specific integrated circuits (ASICs) [5, 6, 7] have been proposed. These algorithms and ASIC designs either rely on idealistic channel-hardening assumptions [5, 6] or deploy approximations [1, 4] to reduce complexity. Unfortunately, both of these simplifications result in high error rates (i) under realistic propagation conditions, such as correlation and per-user path loss, and (ii) in systems where the number of UEs is equal to the number of BS antennas. As a consequence, achieving near-optimal performance in realistic systems necessitates novel data detection algorithms that can be implemented efficiently.

Contributions

We propose the first data detector ASIC that achieves near-MAP performance for 32 UEs under realistic propagation conditions. Furthermore, the ASIC provides soft-input soft-output (SISO) capabilities for iterative detection and decoding. The algorithm builds upon the large-MIMO approximate message passing (LAMA) algorithm [3], which achieves MAP-optimal error-rate performance for Rayleigh fading channels and in the large-antenna limit,

assuming that the UE-to-BS antenna ratio is less than a threshold that depends on the constellation. In contrast to linear data detectors, LAMA exploits information on the constellation to improve performance; for QPSK, for example, LAMA achieves optimal performance in the large-antenna limit and for systems where the number of UE and BS antennas are identical. Since practical systems are finite-dimensional and real-world channels exhibit correlation, we include algorithm-level optimizations to support realistic channels with LAMA. To achieve high throughput at low area, our ASIC uses coarse-grained pipeline interleaving, processing two detection problems within the same architecture. The fabricated 28nm CMOS ASIC outperforms existing designs under realistic channel conditions and for systems in which the number of UEs is comparable to the number of BS antennas.

II Massive MU-MIMO Data Detection

We consider the uplink of a coded massive MU-MIMO system with $U$ single-antenna UEs and $B$ BS antennas. The information bit vectors $\mathbf{b}$ of the $U$ UEs are encoded on a per-UE basis (e.g., using a convolutional code) and the resulting coded bit-stream vectors $\mathbf{x}$ are mapped (using Gray labeling) to a sequence of transmit vectors $\mathbf{s}\in\mathcal{O}^{U}$, where $\mathcal{O}$ corresponds to the constellation of size $2^{Q}$. Each transmit vector $\mathbf{s}$ is associated with $UQ$ binary values $x_{u,q}\in\{0,1\}$, $u=1,\ldots,U$, $q=1,\ldots,Q$, corresponding to the $q$th bit of the $u$th entry (spatial stream) of $\mathbf{s}$. We assume $\operatorname{\mathbb{E}}_{\mathbf{s}}[\mathbf{s}\mathbf{s}^{\textnormal{H}}]=E_{s}\mathbf{I}_{U}$, where $E_{s}$ is the symbol variance. The baseband input-output relation of the MU-MIMO channel is modeled as $\mathbf{y}=\mathbf{H}\mathbf{s}+\mathbf{n}$, where $\mathbf{H}\in\mathbb{C}^{B\times U}$ is the MIMO channel matrix, $\mathbf{y}\in\mathbb{C}^{B}$ is the received vector at the BS, and $\mathbf{n}$ is $B$-dimensional i.i.d. zero-mean complex Gaussian distributed noise with variance $N_{0}$ per entry. We assume that $\mathbf{H}$, $N_{0}$, and $E_{s}$ are known at the BS.

II-A Iterative MIMO Decoding

Iterative detection and decoding in MIMO systems achieves near-optimal spectral efficiency in MIMO wireless systems [8]. Reliability information on the coded bits, often expressed as log-likelihood ratios (LLRs), is iteratively exchanged between the MIMO data detector and the channel decoder. In each iteration, a soft-input soft-output (SISO)-capable MIMO data detector computes extrinsic LLRs for the coded bits $x_{u,q}$ as

[TABLE]

using the received vector $\mathbf{y}$ and a-priori LLRs $\Lambda^{\text{prior}}_{u,q}$, $u=1,\ldots,U$, $q=1,\ldots,Q$, obtained from the channel decoder. The extrinsic LLRs $\Lambda^{\textnormal{d}}_{u,q}$, which represent reliability estimates for each coded bit $x_{u,q}$, are then passed to the channel decoder, which computes new a-priori LLRs $\Lambda^{\textnormal{prior}}_{u,q}$, $\forall u,q$, that are used by the MIMO data detector in the next iteration. After a small number of iterations $I$, the channel decoder generates final decisions $\hat{}\mathbf{b}$ for the information bit vector $\mathbf{b}$.

II-B *Hardware Friendly LAMA Algorithm *

LAMA is an efficient data detection algorithm based on approximate message passing (AMP), that is provably optimal (in terms of error-rate performance) in the large-system limit (i.e., fix $\beta=B/U$ and $B\to\infty$) with i.i.d. Rayleigh fading channels [3]. In each of its $t_{\textnormal{max}}$ iterations, LAMA decouples the MIMO system into parallel and independent AWGN channels with equal signal-to-interference-plus-noise ratio (SINR). As a result, LAMA optimally denoises the parallel AWGN channels in every iteration, which successively increases the post-equalization SINR and improves the error-rate performance.

To deal with realistic channel conditions (such as correlation and per-UE path loss), we apply algorithm-level modifications to the original LAMA algorithm in [3]. First, we transform LAMA so that it operates on the $U\times U$ dimensional Gram matrix $\mathbf{G}=\mathbf{H}^{\textnormal{H}}\mathbf{H}$, instead of the $B\times U$ channel matrix $\mathbf{H}$, which reduces the per-iteration complexity. Second, we deploy message damping techniques [9] to reduce the performance loss of LAMA in finite-dimensional systems that exhibit correlation and large-scale UE fading. Specifically, we damp the updates of $\hat{\tau}^{t}$ and $\rho^{t}$ by a factor $\theta\in(0,1]$, i.e., we use $\hat{\tau}^{t}_{\text{d}}$ instead of $\hat{\tau}^{t}$ in line 6 of \frefalg:LAMA, and $\hat{\tau}^{t}_{\text{d}}=\theta\hat{\tau}^{t}+(1-\theta)\hat{\tau}^{t-1}_{\text{d}}$ . Third, we include support for iterative detection and decoding. The implemented LAMA algorithm is summarized in \frefalg:LAMA (message damping details are excluded). The functions $\mathsf{F}$ and $\mathsf{G}$ correspond to the posterior mean and variance applied element-wise, i.e., $\mathsf{F}(z,\rho,\Lambda^{\text{prior}})=\operatorname{\mathbb{E}}_{S}(S|z=S+\rho^{-1/2}N)$, $N\sim\mathcal{C}\mathcal{N}(0,1)$ and $p(S)$ can be derived from the a-priori LLRs $\Lambda^{\text{prior}}$; $\mathsf{G}$ can be derived similarly—see [3] for the details.

III VLSI architecture

\fref

fig:blk_detailed depicts the top-level architecture of the LAMA data detector. LAMA performs two main tasks per iteration: The first task estimates the mean and variance (MV) of the data transmitted by each UE; the second task cancels interference (IC) among the UEs—both of these tasks are detailed below. To maximize throughput, two independent detection problems are processed simultaneously in a pipeline-interleaved manner, i.e., one problem per task. The two main processing units, namely MV and IC, perform the assigned computations in $T_{\textnormal{s}}$ clock cycles, and the results of both units are exchanged for further processing in the subsequent iteration. In the last $t_{\textnormal{max}}$ iteration, the outputs from the IC unit are sent to the LLR computation unit, which takes $T_{\textnormal{LLR}}$ clock cycles. Thus, LAMA delivers a new set of $UQ$ LLR values at a sustained throughput of

[TABLE]

The final design supports $32$ UEs, which requires $T_{\textnormal{s}}=36$ clock cycles and $T_{\textnormal{LLR}}=1$ clock cycle.

III-A Mean and Variance Estimation (MV) Unit

In the first task (line 5 in \frefalg:LAMA), the MV unit receives estimates of the UE’s data and the associated SINR to compute mean and variance values. As shown in \freffig:F_original, a straightforward MV unit would require a large number of multipliers. Although statistical independence in the real and imaginary parts of the transmitted constellation points simplifies computation from $M^{2}$-QAM to two $M$-PAM constellations, mean and variance computation for $16$-PAM (to support 256-QAM) still requires $16$ likelihood function units and a division, resulting in high complexity. Furthermore, the intrinsic LLR values obtained from the channel decoder must be transformed from bit-domain to symbol-domain for SISO processing. To reduce complexity, existing ASICs [5, 7, 6] use hard-symbol clipping or linear approximations, and do not provide support for SISO processing. However, accurate message mean and variance computation is key to support realistic channels and systems with a comparable number of UEs and BS antennas.

To accurately compute the message mean and variance at low complexity, we (i) compute all quantities in the bit-domain, (ii) exploit Gray-mapping symmetries, and (iii) use the max-log approximation.

The conversion into the bit-domain and the max-log approximation only requires $4$ log-likelihood functions for $16$-PAM, instead of $16$ functions in the symbol domain. In addition, we avoid the need of a division per UE by using a LUT-based $\text{tanh}(\cdot)$ function as in [8] with 7 input bits.

The resulting architecture, depicted in \freffig:F_new, also avoids the need of a division per UE. Furthermore, the architecture naturally supports SISO processing for iterative MIMO decoding. Our simulations in \frefsec:PERperf for various antenna configurations and channel models show that our approach entails a negligible performance loss at around $4\times$ lower area.

III-B Interference Cancellation (IC) Unit

In the second task (line 6 in \frefalg:LAMA), the IC unit performs interference cancellation and updates the SINR.

III-B1 $32$-MAC matrix-vector multiplication

Interference cancellation requires a $32\times 32$ complex-valued matrix-vector multiplication, which we compute sequentially in $32$ clock cycles using a linear array of $32$ complex-valued multiply-accumulate (MAC) units in a column-by-column fashion. To minimize the critical path caused by the large fan-out of a conventional linear array of MAC units, \freffig:cannon shows a simplified version of Cannon’s algorithm [10], which circularly shifts the array’s input vector while sequentially processing rows of the matrix over multiple clock cycles; this reduces the vector memory fan-out from 32 MAC units to one MAC unit and a register. To further reduce the critical path and simplify placement, each row of the Gram matrix is stored next to each MAC unit with standard-cell-based latch-arrays.

III-B2 SINR computation

The post-equalization SINR is computed in parallel using a Newton-Raphson (NR) reciprocal unit [8]. We first shift the input $x$ according to $\bar{x}=2^{\alpha}x$, $\alpha\in\mathbb{Z}$ so that $\bar{x}\in[0.5,1)$, resulting in high numerical stability. Based on an initial guess obtained from a look-up table, a single NR iteration is sufficient to compute $\bar{y}_{1}\simeq\bar{x}^{-1}$; the final result $y=2^{\alpha}\bar{y}_{1}$ corresponds to an approximation of $x^{-1}$.

IV Implementation Results and Comparison

Figs. 6 and 6 show the PER of our LAMA ASIC in comparison with the linear minimum-mean squared-error (MMSE) equalizer and channel hardening-exploiting message passing (CHEMP) algorithm [4]. The number of algorithm iterations are indicated after the dash; e.g., LAMA$-14$ represents LAMA with 14 iterations. Outer iterations over the channel decoder are shown as either none ($I=0$; solid lines) or one ($I=1$; dashed lines) iteration.

We simulate an LTE-based massive MU-MIMO-OFDM system at $f_{c}=2$ GHz with 1200 active subcarriers and per-user convolutional coding with rate $R$. We use two channel models: (a) Rayleigh fading and (b) WINNER II typical urban micro [11] to model a realistic propagation environment. For a typical $256\times 32$ ($B\times U$) massive MU-MIMO scenario, LAMA achieves the same performance as linear MMSE, but avoids a matrix inversion; CHEMP suffers an error floor above 10$\%$ PER. For the challenging $32\times 32$ system, LAMA significantly outperforms the linear MMSE detector, achieving more than $11$ dB SNR improvements for the typical urban micro channel; CHEMP fails to successfully detect packets. Extensive numerical simulations have been carried out to determine the ASIC’s fixed-point parameters; the implemented design achieves near-floating-point performance.

IV-A Implementation Results

\fref

fig:chip shows a micrograph of the fabricated and fully-functional 28nm CMOS ASIC with the LAMA detector core highlighted. The LAMA ASIC only occupies $0.37$ mm2; the rest of the chip contains unrelated designs. The clock signal was generated by a VLSI test system and directly fed into the ASIC. At nominal supply of $0.9$ V at $300$ K, the ASIC reaches a maximum measured clock frequency of $400$ MHz at $151$ mW, which results in $354$ Mb/s for $32$ UEs transmitting $256$-QAM.

\fref

fig:measurements shows measured energy-efficiency in pJ/bit obtained via voltage-frequency scaling. By reducing the supply close to the threshold voltage, the detector achieves optimal energy-efficiency: at $0.35$ V we have $123$ pJ/bit (achieving $2.66$ Mb/s). If maximum throughput is desired, one can increase the supply to $1.15$ V and obtain $511$ Mb/s (at $670$ pJ/b efficiency).

\fref

tbl:comparison compares LAMA to state-of-the-art massive MU-MIMO data detectors. Our LAMA ASIC achieves more than $4\times$ improved normalized area efficiency than [7], which computes a matrix inversion. Although LAMA achieves lower area efficiency (in Gb/s/$\text{mm}^{2}$) than the detectors in [5, 6], these designs suffer an error floor higher than LTE specifications under realistic channel conditions (cf. Figs 6 and 6). We note that the nominal energy efficiency is inferior to other designs due to increased arithmetic precision requirements in support of realistic channel conditions and symmetric massive MU-MIMO systems. To the best of our knowledge, the proposed LAMA ASIC is the first silicon prototype of a $32$-UE massive MU-MIMO data detector that provides near-optimal error rates under realistic propagation conditions and for symmetric systems. Both of these advantages are critical to BS providers as one can support up to 32 UEs with relatively small ($B\geq 32$) BS antenna arrays under realistic channel conditions.