# A 354Mb/s 0.37mm^2 151mW 32-User 256-QAM Near-MAP Soft-Input Soft-Output Massive MU-MIMO Data Detector in 28nm CMOS

## TL;DR

This paper introduces a highly efficient 28nm CMOS ASIC for massive MU-MIMO systems, enabling 32-user 256-QAM detection with near-optimal performance, low power, and high throughput, suitable for real-world wireless applications.

## Contribution

It presents a novel hardware implementation of a modified LAMA algorithm for massive MU-MIMO detection, achieving high throughput and energy efficiency in a compact chip.

## Key findings

- Achieves 354Mb/s throughput at 151mW power consumption.
- Improves SNR by over 11dB compared to existing detectors.
- Provides 4x higher throughput per area than recent message-passing detectors.

## Abstract

This paper presents a novel data detector ASIC for massive multiuser multiple-input multiple-output (MU-MIMO) wireless systems. The ASIC implements a modified version of the large-MIMO approximate message passing algorithm (LAMA), which achieves near-optimal error-rate performance (i) under realistic channel conditions and (ii) for systems with as many users as base-station (BS) antennas. The hardware architecture supports 32 users transmitting 256-QAM simultaneously and in the same time-frequency resource, and provides soft-input soft-output capabilities for iterative detection and decoding. The fabricated 28nm CMOS ASIC occupies 0.37mm^2 , achieves a throughput of 354Mb/s, consumes 151mW, and improves the SNR by more than 11dB compared to existing data detectors in systems with 32 BS antennas and 32 users for realistic channels. In addition, the ASIC achieves 4x higher throughput per area compared to a recently proposed message-passing detector.