Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

TL;DR

This paper presents an analytical model for interface charge traps in junctionless FETs that accounts for temperature effects from 77K to 400K, validated against numerical simulations across various operation regions.

Contribution

It introduces a novel predictive charge-based model for interface traps in junctionless FETs that includes temperature dependence, validated through extensive simulations.

Findings

Model accurately predicts charge trap effects across temperature range

Validates against TCAD simulations in all operation regions

Demonstrates impact of traps on device characteristics

Abstract

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.

Figures

Equations

$$Q_{it}=-q\underset{E_V}{\overset{E_C}{\int }}{D}_{it}(E)\times f(E)dE.$$

$$Q_{sc}=-2C_{ox}\left(V_{GS}-\Delta {\varphi }_{ms}-{\psi }_s+\frac{Q_T}{C_{ox}}\right),$$

$$V_{GS}=\Delta {\varphi }_{ms}+{\psi }_s-\frac{Q_{sc}+2Q_T}{2C_{ox}}.$$

$$V_{GS}^{\prime }=\Delta {\varphi }_{ms}+{\psi }_s-\frac{Q_{sc}}{2C_{ox}}.$$

$$\Delta V_{GS}=\frac{-Q_{it}}{C_{ox}}+\frac{-Q_{ot}}{C_{ox}}.$$

$$f(E_{it}{)}^{-1}=1+\exp \left(\frac{E_{it}-E_F}{k_{B}T}\right).$$

$$\frac{Q_{it}}{q{N}_{it}}=-{\left[1+\exp \left(\frac{E_{t-i}}{k_{B}T}\right)\exp \left(-\frac{{\psi }_s-V_{ch}}{U_T}\right)\right]}^{-1},$$

$$\begin{split}E_{s}^{2}&=\frac{2qn_{i}U_{T}}{\epsilon_{si}}\Biggl{[}\exp\left({\frac{\psi_{s}-V_{ch}}{U_{T}}}\right)-\exp\left({\frac{\psi_{0}-V_{ch}}{U_{T}}}\right)\\ &-\frac{N_{D}}{n_{i}}\left(\frac{\psi_{s}-\psi_{0}}{U_{T}}\right)\Biggr{]},\end{split}$$

$$\psi_{s}-\psi_{0}=\frac{qn_{i}T_{sc}^{2}}{8\epsilon_{si}}\Biggl{[}\exp\left({\frac{\psi_{0}-V_{ch}}{U_{T}}}\right)-\frac{N_{D}}{n_{i}}\Biggr{]},$$

$$\begin{split}\left(\frac{Q_{sc}}{2\epsilon_{si}}\right)^{2}&\!\!\!=\frac{2qn_{i}U_{T}}{\epsilon_{si}}\Biggl{\{}\!\exp\left({\frac{\psi_{0}-V_{ch}}{U_{T}}}\right)\!\!\left[\exp\left({\frac{\psi_{s}-\psi_{0}}{U_{T}}}\right)\!-1\right]\\ &-\frac{N_{D}}{n_{i}}\left(\frac{\psi_{s}-\psi_{0}}{U_{T}}\right)\Biggr{\}}.\end{split}$$

$${\left(\frac{Q_{sc}}{2{ϵ}_{si}}\right)}^2=\frac{2q{N}_D}{{ϵ}_{si}}\left({\psi }_0-{\psi }_s\right).$$

$${\psi }_s-V_{ch}=U_T\ln \left(\alpha \theta \right),$$

$$\alpha =\frac{N_D}{n_i}\exp \left(-\frac{Q_{sc}^2}{8U_T{C}_{si}{Q}_f}\right),$$

$$\theta =1-{\left(\frac{Q_{sc}}{Q_f}\right)}^2,$$

$$\Delta V_{GS}=\frac{q{N}_{it}}{C_{ox}\left(1+\eta {\alpha }^{-1}{\theta }^{-1}\right)},$$

$$Q_{sc}=-2C_{ox}\left(V_{GS}^{\ast }-\Delta V_{GS}-V_{ch}-U_T\ln \left(\alpha \theta \right)\right),$$

$$\alpha =\frac{N_D}{n_i}\exp \left(-\frac{Q_f}{8U_T{C}_{si}}\right).$$

$$\Delta V_{th}=\frac{q{N}_{it}}{C_{ox}(1+\eta {\alpha }^{-1})}.$$

$${\psi }_0\approx {\psi }_{0_{FB}}=V_{ch}+U_T\ln \left(\frac{N_D}{n_i}\right).$$

$${\left(\frac{Q_{sc}}{2{ϵ}_{si}}\right)}^2=\frac{2q{n}_i{U}_T}{{ϵ}_{si}}\left[\exp \left(\frac{{\psi }_s-V_{ch}}{U_T}\right)-\frac{N_D}{n_i}\right].$$

$${\psi }_s-V_{ch}=U_T\ln \left(\beta \right),$$

$$\beta =\frac{Q_{sc}^2}{8{ϵ}_{si}q{n}_i{U}_T}+\frac{N_D}{n_i}.$$

$$\Delta V_{GS}=\frac{q{N}_{it}}{C_{ox}\left(1+\eta {\beta }^{-1}\right)},$$

$$Q_{sc}=-2C_{ox}\left(V_{GS}^{\ast }-\Delta V_{GS}-V_{ch}-U_T\ln \left(\beta \right)\right).$$

$$\Delta V_{GS}=\frac{q{N}_{it}}{C_{ox}\left(1+\eta {\gamma }^{-1}\right)},\gamma =\{\begin{array}{ll}\alpha \theta ,& \text{mbox}Depletion\\ \beta ,& \text{mbox}Accumulation\end{array}.$$

$$Q_m=-Q_f-2C_{ox}\left(V_{GS}^{\ast }-\Delta V_{GS}-V_{ch}-U_T\ln (\gamma )\right).$$

$$\begin{split}&I_{Dep}\left(V^{*}_{G},V_{D},V_{S}\right)\!=\!\mu\frac{W}{L_{G}}\Biggl{[}\!\left(\frac{1}{8C_{si}}-\frac{1}{4C_{ox}}\right)\!Q_{sc}^{2}\!-\!\frac{Q_{sc}^{3}}{12Q_{f}C_{si}}\\ &+\left(\frac{Q_{f}}{2C_{ox}}+2U_{T}\right)Q_{sc}-U_{T}Q_{f}\ln\left(1+\frac{Q_{sc}}{Q_{f}}\right)^{2}\Biggr{]}^{D}_{S},\end{split}$$

$$\begin{split}&I_{Acc}\left(V^{*}_{G},V_{D},V_{S}\right)\!=\!\mu\frac{W}{L_{G}}\Biggl{[}\left(\frac{Q_{f}}{2C_{ox}}+2U_{T}\right)Q_{sc}-\frac{1}{4C_{ox}}Q_{sc}^{2}\\ &-U_{T}Q_{f}\ln\left(1+\frac{Q_{sc}^{2}}{8Q_{f}C_{si}U_{T}}\right)\\ &-2U_{T}\sqrt{8Q_{f}C_{si}U_{T}}\arctan\left(\frac{Q_{sc}}{\sqrt{8Q_{f}C_{si}U_{T}}}\right)\Biggr{]}^{D}_{S},\end{split}$$

$$\begin{array}{rl}& I_{hyb}\left(V_G^{\ast },V_D,V_S\right)=I_{Acc}\left(V_G^{\ast },V_G^{\ast }-V_{FB},V_S\right)\\ & +I_{Dep}\left(V_G^{\ast },V_D,V_G^{\ast }-V_{FB}\right).\end{array}$$

$$I_D=\frac{W}{L_g}\mu Q_m{V}_{DS},$$

Full text

{IEEEkeywords}

Interface traps, charge-based model, double-gate junctionless FET, ionizing radiation, aging effects, biosensors, temperature.

1 Introduction

\IEEEPARstart

Junctionless field-effect transistors (JLFET) were proposed as a promising device for the future of scaling. Actually, source/drain (S/D) junctions in conventional metal-oxide-semiconductor field-effect transistors (MOSFET) is a big challenge in the nanoscale dimension [1]. The main advantage of JLTs is that they overcome this step and still are fully compatible with CMOS technology. In addition, JLFET is a good option for label-free biosensors when shoped as nanowires [2].

Using JLFET as biosensors, called Nanowires (NWs), is an interesting option due to their proven high sensitivity to biological and chemical elements [3]. They share the same principle of operation with regular JLFETs, except that they do not have any solid-state gate over the insulator. Because of this feature, they are exposed to contaminants from the materials which they are in contact with. Hence, these devices are facing much more defects or interface charge traps than the state-of-the-art CMOS devices, a situation that may affect their electrical properties. Similarly, trap and defects can be generated by ionizing radiation just as in regular MOSFETs.

When a MOSFET is exposed to high-energy ionizing radiation, deep trap states are generated in the bulk oxide or near the Si/oxide interface. The process of traps generation depends on the temperature, the applied electric field, and the oxide thickness [4] and [5]. Aging mechanism in MOS technologies is also a common cause of traps creation at the Si/oxide interface [6] and [7]. These interface traps could degrade the performance of MOS devices.

Modeling the effect of radiation on inversion mode MOSFETs has already addressed in [8], but that model is not appropriate for junctionless devices. Influence of interface charge traps on biosensor junctionless devices was discussed in [3].

Thus, in order to account for ionizing radiation, stress-induced defects as well as the effect of interface charge traps on JLFETs in a simple and compact model compatible approach, we propose analytical expressions for modeling the interface charge traps in Double-Gate JLFET (DG JLFET), and we also include the effect of temperature from $77\text{\,}\mathrm{K}$ to $400\text{\,}\mathrm{K}$. This model relies on the charge-based approach in [9] where we derive an equivalent gate-source voltage ($\Delta V_{gs}$) to take into account the effect of interface charge traps. This is quite different from former developments [3]. We study the behavior of current-voltage characteristics and derive analytical solution for the subthreshold swing (SS). This approach will be validated with technology computer-aided design (TCAD) simulations, including temperature.

2 GATE VOLTAGE SHIFT IN PRESENCE OF INTERFACE TRAPS IN JLFETS

As mentioned, high-energy radiation and aging are responsible for ionization damage in the form of oxide charge traps ($Q_{ot}$) and interface charge traps ($Q_{it}$). Traps close to the Si/oxide interface can be charged positively, negatively or neutral. These charge states depend on their energy level respect to the mid-gap energy and Fermi level. When the energy level of the trap is above the mid-gap, it behaves as an acceptor-like trap, and when below the mid-gap, it behaves like a donor-like trap [10] and [11]. A donor-like trap with an energy level above the Fermi level will be positively charged by emitting an electron, and neutral if its energy is below the Fermi level. Conversely, an acceptor-like trap with an energy level above the Fermi level is electrically neutral and will be negatively charged by trapping an electron if its energy is below the Fermi level [3] and [10]. Hence, Interface charge traps are amphoteric and their behavior as donors or acceptors depends on their energy in the band-gap [3], [8]. Fig. 1.a shows the energy diagram of an n-type DG JLFET at flat band voltage. As explained, the donor-like traps are completely filled but the acceptor-like traps are partially filled. Hence, we have negative charges at the Si/oxide interface. Fig. 1.b demonstrates the energy diagram of a p-type DG JLFET at flat band voltage. Acceptor-like traps are completely empty and donor-like traps are partially filled, resulting in positive charges at the interface.

The interface charge density $Q_{it}$ is obtained by integrating the trap-state density $D{it}(E)$ times the trap occupation probability $f(E)$ over the band-gap energy [11],

[TABLE]

We consider an n-type long-channel symmetric double-gate JLFET (as shown in Fig. 1.c) with a doping density $N_{D}$, a channel width and length $W$ and $L_{g}$ respectively, a channel thickness $T_{sc}$ and a gate oxide thickness $t_{ox}$.

The total charge in the semiconductor, $Q_{sc}$, is related to the potential which drops across the gate capacitor

[TABLE]

where $\Delta\phi_{ms}$ denotes the difference between the work function of metal and the work function of an intrinsic semicondoctor, and $Q_{T}$ represents the trap charge density includes interface charge traps and oxide charged traps i.e., $Q_{T}=Q_{it}+Q_{ot}$. We rewrite (2) as follows

[TABLE]

The surface potential only depends on the charge density in the silicon channel ($Q_{sc}$). Hence, by imposing the same charge in the semiconductor, the gate potential in the case there is no trap i.e., $Q_{T}=0$ will be

[TABLE]

Therefore, according to (3) and (4), traps are responsible for a gate-source voltage shift ($\Delta V_{GS}$) equal to $-Q_{T}/C_{ox}$. As expected, two contributions are evidenced

[TABLE]

The oxide charge traps are supposed to have a fixed charge density (i.e. they are not affected by the potentials) meaning that they would merely shift the electrical characteristics by a constant value $-Q_{ot}/C_{ox}$. Therefore, without loss of generality, we propose to focus on the effect of $Q_{it}$ on the electrical characteristics.

Because the continuum nature of traps energy levels, (1) has no analytical solution. Thus, we first investigate the single-level interface traps, then include the common exponential trap energy level distribution.

3 Single Energy Level Traps

We assume an n-type DG JLFET and consider acceptor-like interface traps with a density ($N_{it}$) per unit area at $E_{it}$ which is the energy of single interface charge trap. Hence, for a single trap $(E_{it})$, $D_{it}(E_{it})$ equals to $-q\times N_{it}$ and $Q_{it}$ is given by $Q_{it}=-q\times N_{it}\times f(E_{it})$. The occupation probability of an acceptor-like trap with an energy level $E_{it}$ is determined by [8]

[TABLE]

Here we assume the degeneracy factor equal to 1. By defining $E_{t-i}=E_{it}-E_{i}$, where $E_{i}$ is the intrinsic fermi level, $Q_{it}$ is obtained by

[TABLE]

where $\psi_{s}=-(E_{i}-E_{f})/q$ is the surface potential, $V_{ch}$ is the quasi Fermi potential and $U_{T}=k_{B}T/q$ is the thermal voltage.

Following the derivation of the charge-based model for double-gate JLFETs developed in [9] and [10], we have the two following relationships which link the surface potential ($\psi_{s}$) and the center potential ($\psi_{0}$)

[TABLE]

[TABLE]

where $n_{i}$ is the intrinsic carrier concentration and $\epsilon_{si}$ is the permittivity of silicon. $E_{s}$ is the surface electric field which equals to ${Q_{sc}}/{2\epsilon_{si}}$. Hence, $Q_{sc}$, the semiconductor total charge density can be linked to the surface and center potential, and we can write

[TABLE]

3.1 Depletion Mode

Under depletion mode, the potential at the center is larger than the potential at the surface which leads to a positive charge in the semiconductor ($Q_{sc}\geq 0$). Hence, the exponential term in (10) is much smaller than the second term and therefore relation (10) can be approximated with

[TABLE]

By substituting (9) in (11), the surface potential in the depletion mode is obtained with respect to the total charge density

[TABLE]

where $\alpha$ and $\theta$ are

[TABLE]

[TABLE]

where $Q_{f}=qN_{D}T_{si}$ and $C_{si}=\epsilon_{si}/T_{sc}$.

Unlike oxide charge traps, interface charge traps can cause a gate-source voltage shift that depends on the total charge density. By introducing (12) in (7) and then in (5) (with $Q_{ot}=0$), the gate-source voltage shift is

[TABLE]

where $\eta=\exp(E_{t-i}/k_{B}T)$. Hence, the total charge density in the semiconductor becomes

[TABLE]

where we define the effective gate voltage as $V_{GS}^{*}=V_{GS}-\Delta\phi_{ms}$. By solving relationships (15) and (16), total charge density in the semiconductor and the mobile charge density $Q_{m}=Q_{sc}-Q_{f}$, are obtained. It is worth mentioning that, when there are not traps i.e., $Q_{T}=0$, $\Delta V_{GS}$ is zero and relationship (16) gives back the general relationship derived in [9] and [10].

3.2 Threshold Voltage Shift

Unlike inversion mode MOSFETs, the definition of threshold voltage ($V_{th}$) in junctionless transistors is not obvious. However, there are some definitions of threshold voltage for junctionless transistors. One of these defines the threshold voltage as the gate potential which cancels the mobile charge density ($Q_{sc}=Q_{f}$) when the logarithmic term in (16), i.e. $\theta$ is neglected [10]. Hence, $\alpha$ at threshold takes a simple form

[TABLE]

Under these assumptions, the threshold voltage shift is

[TABLE]

3.3 Accumulation Mode

In accumulation mode, the second term in (5) is always smaller than the exponential term. Therefore, the second term in accumulation can be omitted. In addition, in accumulation the center potential remains close to the value it takes at the flat-band condition [10]

[TABLE]

Thus, relation (10) can be simplified to

[TABLE]

Hence, the surface potential in the accumulation mode is derived and is a function of the total charge density

[TABLE]

where $\beta$ is defined as

[TABLE]

Introducing (21) in (7) and then in (5) (with $Q_{ot}=0$) results in the gate-source voltage shift in accumulation mode

[TABLE]

and the total charge density in the semiconductor in accumulation mode becomes

[TABLE]

Comparing (15) with (23), we notice that $\Delta V_{GS}$ is given by the same relationship for both regions of operation, an unexpected but very interesting result which can be summarized as follows

[TABLE]

This implies that the mobile charge density satisfies a generic relationship,

[TABLE]

To confirm the validity of this model, we performed simulations with SILVACO TCAD software assuming a double gate JLFET with $1\text{\,}\mathrm{\SIUnitSymbolMicro}\mathrm{m}$ channel length and $10\text{\,}\mathrm{n}\mathrm{m}$ silicon thickness. The doping density and oxide thickness were set respectively to $N_{D}$ = $5\text{\times}{10}^{16}\text{\,}\mathrm{c}\mathrm{m}^{-3}$ and $1.5\text{\,}\mathrm{n}\mathrm{m}$.

Here the single energy level has been activated for the traps. The interface trap density is set to $N_{it}$ = $1\text{\times}{10}^{12}\text{\,}\mathrm{c}\mathrm{m}^{-2}$. The mobile charge density versus effective gate voltage which is obtained from TCAD simulations and the model is depicted in Fig. 2.a. Lines and symbols have been used for the analytical model and TCAD simulations, respectively. Both linear and logarithmic representations of the analytical model demonstrate a full agreement with TCAD simulations.

3.4 Drain Current

Since we have analytical relationships for mobile charge density in depletion and accumulation modes, we can use both analytical charge-based model described in [9] and explicit relationships which are derived in [12] for obtaining drain current. To assess this model with TCAD simulations, we have used explicit relationships and we recall them here. Thus for the drain current in the depletion mode we have the following equation from [12]

[TABLE]

and for the accumulation mode [12]

[TABLE]

where $\mu$ is the free carrier mobility. If we define the hybrid channel when some part of the channel, near the source contact, is in accumulation and the other part, near the drain, is in depletion, we can write the drain current as follows [12]

[TABLE]

In this work $\mu$, is assumed constant along the channel and the width of the device is set to $1\text{\,}\mu\mathrm{m}$.

By solving (26) and intruducing it in (27) to (29) the drain current is obtained. The drain current versus the effective gate voltage at $V_{DS}$ = $10\text{\,}\mathrm{m}\mathrm{V}$ and $V_{DS}$ = $1\text{\,}\mathrm{V}$ for the trap energy levels $E_{t-i}$ = $0\text{\,}\mathrm{e}\mathrm{V}$ and $E_{t-i}$ = $0.2\text{\,}\mathrm{e}\mathrm{V}$ has been plotted in Fig. 2.b and 2.c. The results from the model are compared with TCAD simulations using the same parameters and indicate a good agreement in both linear and exponential representations.

The black dashed line in all the figures depicts the case which the density of traps is zero i.e. without traps. In order to make the effect of interface traps more clear, gate voltage shift due to the interface traps as a function of effective gate voltage for different values of energy levels has been shown in Fig. 3.a. The agreement between the analytical model and TCAD simulations is excellent in both depletion and accumulation modes. It is observed from the plot that $\Delta V_{GS}$ for above the flatband voltage doesn’t depend on the $E_{t-i}$ and it can be simplified to $\Delta V_{GS}=qN_{it}/C_{ox}$.

3.5 Subthreshold Swing

Subthreshold swing degradation is another important effect of interface charge traps since they implicitly change the charge density with voltages. In subthreshold regime, saturation is reached at low drain-to-source voltages (about $4U_{T}$). By assuming that the mobile charge density at low $V_{DS}$ is almost constant along the channel from source to drain, the current can be approximated by

[TABLE]

and the subthreshold swing ($SS$) becomes

[TABLE]

where ${\partial V_{GS}}/{\partial Q_{m}}$ derived from (26):

[TABLE]

where $\gamma^{\prime}=\partial\gamma/\partial Q_{m}$. Since the device operates in subthreshold, according to relation (25) $\gamma$ is equal to $\alpha\theta$ and $\gamma^{\prime}/\gamma$ becomes

[TABLE]

Next, introducing (33) in (32) then substituting in (31), the subthreshold swing becomes an explicit function of the mobile charge density:

[TABLE]

To extract the maximum subthreshold swing ($SS_{max}$), we propose to introduce some approximation in (34). Since $Q_{m}$ is negligible in the subthreshold, we can ignore $Q_{m}/(2Cox)$ and assume that $Q_{m}\gamma^{\prime}/\gamma$ is close to unity:

[TABLE]

Thus, $SS$ peaks when $\gamma=\eta$

[TABLE]

Interestingly, the largest value of the subthreshold slope is closely related to the density of interface traps.

Subthreshold swing degradation induced by the presence of interface traps can be observed in Fig. 2. To make more clear this effect, subthreshold swing as a function of the effective gate potential for different values of $E_{t-i}$ and $N_{it}$ for both the analytical model and TCAD simulations, have been plotted in Fig. 3.a and 3.b. The agreement between the analytical solution and the TCAD simulations is evidenced.

4 Exponential Trap Energy Level Distribution

So far only considered discrete energy trap levels have been discussed. Although these are instructive, they are not representative of real devices. Admittedly, real devices exhibit an exponential distribution of traps energy in the bandgap, commonly designed as U-shaped distribution [13].

Since we assume an n-type device, only interface traps which energies above the midgap are considered. In addition, according to the TCAD models, the maximum in the acceptor-like density lays at the conduction band edge. Hence, the charge density of traps can be written

[TABLE]

where $N_{itc}$ is the density of acceptor-like states in the exponential distribution at the conduction band edge and $E_{d}$ specifies the characteristic decay energy.

To calculate the trapped charge density, we rely on the same model discussed in section 3 valid for for single trap energy levels where we simply propose to replace $N_{it}$ and $E_{t-i}$ with averaged parameters $N_{it}^{*}$ and $E_{t-i}^{*}$:

[TABLE]

The analytical approach is compared with TCAD simulations as shown in Fig. 4. Using $N_{itc}$ = $4\text{\times}{10}^{13}\text{\,}\mathrm{c}\mathrm{m}^{-2}$ and $E_{d}$ = $0.035\text{\,}\mathrm{e}\mathrm{V}$ as reported in [3], Then by adjusting the averaged parameters, $N_{it}^{*}$ = $1.5\text{\times}{10}^{12}\text{\,}\mathrm{c}\mathrm{m}^{-2}$ and $E_{t-i}^{*}$ = $0.592\text{\,}\mathrm{e}\mathrm{V}$. These values fit quite well with TCAD results. Interestingly, these parameters which were ’extracted’ at room temperature still give accurate results when changing the temperature. Fig. 4 illustrates the drain current versus the effective gate potential at $V_{DS}$ = $10\text{\,}\mathrm{m}\mathrm{V}$ and $V_{DS}$ = $1\text{\,}\mathrm{V}$ for an exponential distribution of interface traps energy. Since the maximum density of interface traps happens close to the conduction band edge, their impact on the electrical characteristic is evidenced at relatively high gate potentials, otherwise traps remain unoccupied.

5 Assessment of the Model from 77K to 400K

In some applications, low temperature operation is necessary and present many advantages such as a steeper subthreshold slope [14, 15, 16]. Having an analytical model covering a wide range of temperature operation is therfore a big advantage.

In this section, we assess the model for various temperatures ranging from $77\text{\,}\mathrm{K}$ to $400\text{\,}\mathrm{K}$ (note that we have used Boltzmann statistics only). For simplicity, we also assume a constant mobility, given that this will mainly act as a scaling factor for the current, but will have almost no impact on the electrostatics, i.e. on the conclusions of this section [17]. According to [18] the mobility at low temperatures changes with respect to the mobile charge density. This effect could be introduced in the proposed model at the correction to the current, however, the conclusions on the trap charge distribution will remain the same. In addition, this would require introducing fitting parameters, which would weaken our physics-based analysis. The intrinsic carrier concentration for the temperatures used in this section are $n_{i}$ = $4.39\text{\times}{10}^{-13}\text{\,}\mathrm{m}^{-3}$, $1.18\text{\times}{10}^{11}\text{\,}\mathrm{m}^{-3}$, and $6.16\text{\times}{10}^{18}\text{\,}\mathrm{m}^{-3}$ at $T$ = $77\text{\,}\mathrm{K}$, $200\text{\,}\mathrm{K}$, and $400\text{\,}\mathrm{K}$ respectively.

Fig. 5 depicts the mobile charge density versus the effective gate voltage at $T$ = $77\text{\,}\mathrm{K}$, $200\text{\,}\mathrm{K}$, and $400\text{\,}\mathrm{K}$ for single trap energy levels $E_{t-i}$ = $0\text{\,}\mathrm{e}\mathrm{V}$ and $E_{t-i}$ = $0.2\text{\,}\mathrm{e}\mathrm{V}$. For the range of mobile charge density considered, which is depicted in Fig. 5, different trap energy levels behave in the same way at $77\text{\,}\mathrm{K}$. Indeed for those energy levels the traps do not change their charge states. The results confirm an excellent agreement between the analytical model and TCAD simulations.

Finally, we also assessed the validity of the model for the more realistic case of an exponential energy trap distribution at $T$ = $77\text{\,}\mathrm{K}$, $200\text{\,}\mathrm{K}$, and $400\text{\,}\mathrm{K}$. These are shown in Fig. 6 where the drain current versus the effective gate voltage is plotted at $V_{DS}$ = $10\text{\,}\mathrm{m}\mathrm{V}$ and $V_{DS}$ = $1\text{\,}\mathrm{V}$. Interestingly, the averaged parameters, i.e., $N_{it}^{*}$ and $E_{t-i}^{*}$ do not need to be modified, meaning that the model that we have presented is quite predictive (note that we anticipate that for lower temperatures i.e. $4.2\text{\,}\mathrm{K}$ the roots of the model would have to be revised introducing Fermi-Dirac Statistics, and possibly 2D density of states).

6 Conclusion

An analytical charge-based model for symmetric double-gate junctionless FETs with interface charge traps was developed. The model incorporates the impact of radiation and aging degradation on DC electrical characteristics of double-gate JLFETs by proposing an equivalent gate-source voltage. A detailed study of the interface charge traps and their influence on the device performance is carried out. Both single energy level and exponential distribution energy levels for interface traps have been investigated. In particular, the subthreshold swing degradation in the presence of single level interface charge traps has been modelled accurately. We also included the impact of the temperature from $77\text{\,}\mathrm{K}$ to $400\text{\,}\mathrm{K}$, a very important aspect for cryogenic applications. The model has been compared to TCAD simulations with an excellent agreement in all regions of operation from deep depletion to accumulation and linear to saturation.