# Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

## TL;DR

This paper presents an analytical model for interface charge traps in junctionless FETs that accounts for temperature effects from 77K to 400K, validated against numerical simulations across various operation regions.

## Contribution

It introduces a novel predictive charge-based model for interface traps in junctionless FETs that includes temperature dependence, validated through extensive simulations.

## Key findings

- Model accurately predicts charge trap effects across temperature range
- Validates against TCAD simulations in all operation regions
- Demonstrates impact of traps on device characteristics

## Abstract

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.