On the Optimal Refresh Power Allocation for Energy-Efficient Memories

TL;DR

This paper introduces an optimization framework for allocating refresh power in DRAM to minimize error while reducing power consumption, especially beneficial for high-capacity and mobile memory devices.

Contribution

It formulates a convex optimization model for optimal refresh power allocation and an integer programming approach for discrete refresh intervals, achieving significant power savings.

Findings

Optimized refresh intervals reduce power by 29% at 50dB SNR.

The convex model guarantees optimal power allocation under error constraints.

Numerical results demonstrate improved energy efficiency in DRAM.

Abstract

Refresh is an important operation to prevent loss of data in dynamic random-access memory (DRAM). However, frequent refresh operations incur considerable power consumption and degrade system performance. Refresh power cost is especially significant in high-capacity memory devices and battery-powered edge/mobile applications. In this paper, we propose a principled approach to optimizing the refresh power allocation. Given a model for the bit error rate dependence on power, we formulate a convex optimization problem to minimize the word mean squared error for a refresh power constraint; hence we can guarantee the optimality of the obtained refresh power allocations. In addition, we provide an integer programming problem to optimize the discrete refresh interval assignments. For an 8-bit accessed word, numerical results show that the optimized nonuniform refresh intervals reduce the refresh power by 29% at a peak signal-to-noise ratio of 50dB compared to the uniform assignment.

Tables

Table 1. TABLE I: Resource and Fidelity Metrics for Refresh Operation

	Single bit	$B$-bit word
Variable	$t$	$𝐭=(t_0,\dots ,t_{B-1})$
Refresh power	$\frac{1}{t}$	${\sum }_{b=0}^{B-1}\frac{1}{t_b}$
Fidelity	$g\left(t\right)$	${\sum }_{b=0}^{B-1}{4}^{b}g\left(t_b\right)$

Equations

$$p=\mathrm{Pr}\left(T_{\text{retention}}<t\right),$$

$$P\propto \frac{C}{t},$$

$$\mathsf{P}(\mathbf{t})=\sum _{b=0}^{B-1}\frac{1}{t_b}.$$

$$p_b=g(t_b)$$

$$\mathsf{MSE}(\mathbf{t})=\sum _{b=0}^{B-1}{4}^{b}g(t_b),$$

$$p_b=g(t_b)=\alpha \exp (\beta t_b),$$

$$\underset{\mathbf{t}}{\mathrm{minimize}}$$

$$\mathsf{P}(\mathbf{t})=\sum _{b=0}^{B-1}\frac{1}{t_b}\le \mathcal{P}$$

$$t_b\ge \delta ,b=0,\dots ,B-1$$

$$t_b^{\ast }=\{\begin{array}{ll}\delta ,& \text{if}\frac{\nu }{4^b}<\alpha \beta {\delta }^2\exp (\beta \delta );\\ \frac{2}{\beta }W\left(\frac{\beta }{2}\sqrt{\frac{\nu }{4^b\alpha \beta }}\right),& \text{otherwise}\end{array}$$

$$L_1(\mathbf{t},\nu ,\lambda )$$

$$+\nu \left(\sum _{b=0}^{B-1}\frac{1}{t_b}-\mathcal{P}\right)-\sum _{b=0}^{B-1}{\lambda }_b\left(t_b-\delta \right)$$

$${\mathsf{P}}_{\mathsf{max}}=\mathsf{P}=({\mathbf{t}}_0)=\frac{B}{\delta }.$$

$$\mathsf{MS}{\mathsf{E}}_{\mathsf{min}}=\mathsf{MSE}({\mathbf{t}}_0)=\frac{4^B-1}{3}\cdot \alpha \exp (\beta \delta )$$

$$\underset{\mathbf{z}}{\mathrm{minimize}}$$

$$\mathsf{P}(\mathbf{z})=\frac{1}{\gamma \delta }\sum _{b=0}^{B-1}\frac{1}{z_b}\le \mathcal{P}$$

$$z_b\in \mathbb{N},b=0,\dots ,B-1$$

$$\mathsf{PSNR}=10{\log }_{10}\frac{(2^B-1{)}^2}{\mathsf{MSE}}.$$

$$\sum _{b=0}^{B-1}\frac{1}{t_b}$$

$$t_b$$

$$\frac{\partial L_1}{\partial t_b}$$

$${\lambda }_b=4^b\alpha \beta \exp (\beta t_b)-\frac{\nu }{t_b^2}.$$

$${\lambda }_b\left(t_b-\delta \right)=\left(4^b\alpha \beta \exp (\beta t_b)-\frac{\nu }{t_b^2}\right)\left(t_b-\delta \right)=0.$$

$$\alpha \beta t_b^2\exp (\beta t_b)=\frac{\nu }{4^b}$$

Full text

I Introduction

Memory refresh is a periodically repeated procedure that reads and rewrites the data of a memory device to prevent loss of data. It is well known that dynamic random-access memory (DRAM) cells must be refreshed periodically due to charge leakage [1, 2]. A DRAM cell stores one bit of information by controlling the amount of charge on its capacitor. DRAM cells cannot retain their data permanently because of the gradual loss of charge over time. The time a cell can retain its data is called the retention time of the cell. The time interval between refresh operations is the refresh interval, which is the inverse of the refresh rate. A cell that cannot retain its data for the given refresh interval results in a failure, referred to as retention failure (or retention error) [3, 4, 5]. The typical refresh interval in current DRAM standards is $64\text{\,}\mathrm{ms}$, which is a conservative value [4, 5].

The conservative refresh operations lead to high refresh power consumption. This problem is expected to worsen as DRAM device capacity increases [1, 4]. As cell dimension shrinks, memory cells become susceptible to charge leakage and require more frequent refresh operations [5]. Further, the refresh power consumption is critical in battery-powered edge/mobile computing applications. Note that edge/mobile devices are idle most of the time and refresh operations are still required during idle periods unlike write and read operations [6].

Many refresh techniques were proposed to reduce refresh power [3, 7, 8, 2, 4, 5, 6, 9, 10, 11]. Ohsawa et al. [3] and Ghosh et al. [7] proposed architectural techniques to avoid unnecessary refresh operations. Error control coding (ECC) schemes were proposed to decrease refresh rates and correct the resulting retention failures [8, 10, 9, 2]. These ECC schemes suffer from storage or bandwidth overheads. RAIDR [4] allocates different refresh intervals by identifying weak DRAM cells. Flikker [6] specifies critical and non-critical data and refreshes the memory cells storing non-critical data at a lower rate. Cho et al. [11] proposed tiered-reliability memory (TRM) to allocate different refresh intervals depending on the importance of bit positions. Since these previous techniques choose the refresh intervals empirically, the granularity of refresh interval assignments are inherently limited. Further, the optimality of refresh intervals has not been addressed.

We note that refresh is also considered in storage-class memories such as magnetic RAMs (MRAMs) and resistive RAMs (ReRAMs) [12]. For example, MRAMs suffer from high write latency and energy, which are the key drawbacks of MRAM technology. Several techniques [13, 14] attempt to address the write-inefficiency of MRAMs via relaxing retention time and introducing refresh operations. For the sake of concreteness, we focus on DRAM refresh, wherein refresh has been established as a central trade-off between power and fidelity.

This paper presents a principled approach to refresh interval assignments for machine learning (ML) and signal processing tasks. In these applications, the mean squared error (MSE) is a more meaningful fidelity metric than the bit error rate (BER). We formulate a convex optimization problem to minimize the MSE for a given refresh power constraint. Since the formulated problem is convex, the global optimal solutions can be obtained with standard convex programming algorithms. Even more favorably, we derive an analytic expression for the optimal solution using the Karush-Kuhn-Tucker (KKT) conditions. In addition, we formulate a discrete optimization problem by taking into account hardware implementation. Our evaluation shows that the penalty due to discrete intervals is marginal. A prior study in [15] of voltage-swing optimization in static RAMs (SRAMs) is similar in spirit, but its results are not applicable to optimizing DRAM’s refresh intervals. To the best of our knowledge, our work is the first rigorous treatment of the optimal refresh interval assignments, viz. refresh power allocations.

The rest of this paper is organized as follows. Section II explains the current DRAM architecture and refresh operations. Section III introduces the optimization metrics of DRAM’s refresh power and fidelity. Section IV formulates optimization problems to determine the optimum refresh intervals and provides the theoretical analysis. Section V gives numerical results and Section VI concludes.

II DRAM Architecture and Refresh Operations

II-A DRAM Architecture

DRAM system is hierarchically organized channels, modules, ranks, and chips as shown in Fig. 1. Each memory channel drives commands, addresses, and data between a memory controller and one or more DRAM modules [5, 16]. Each module contains multiple DRAM chips that are organized into one or more ranks. A rank consists of multiple chips that operate synchronously to provide a wide data bus (e.g., 64-bit) to increase the bandwidth, as a single DRAM chip is designed to have a narrow data bus width (e.g., 8-bit) [16]. Each of the eight chips in the rank transfers 8 bits simultaneously in a unit interval of double-data rate (DDR) time frame to provide 64 bits of data as shown in Fig. 1LABEL:sub@fig:dram_arch.

A DRAM chip consists of multiple banks that can process DRAM commands independently to increase parallelism. A bank includes a memory array of DRAM cells that are organized into rows and columns, as shown in Fig. 1LABEL:sub@fig:dram_chip [16]. A row consists of $1\text{\,}\mathrm{K}\mathrm{B}$ or $2\text{\,}\mathrm{K}\mathrm{B}$ cells in general and the number of rows depends on the chip capacity.

A cell has (i) a capacitor that stores binary data in the form of stored charge (e.g., charged and discharged states compared to a reference charge represent 1 and 0, respectively), and (ii) an access transistor that serves as a voltage-controlled switch to connect the capacitor to the bitline [5, 16]. DRAM cells in each column share a bitline, which connects them to a sense amplifier. The sense amplifier detects the charge stored in a cell and converts the charge to binary information. DRAM cells in each row share a wire called the wordline, which controls the corresponding cells’ access transistors. When a wordline is enabled by the row decoder, the entire cells in the row get connected to the sense amplifiers through the bitlines, enabling the sense amplifiers to detect the data and latch them into the row buffer [16]. A chunk of the data in the row buffer is fetched out by the column decoder.

II-B Refresh Operations

Since a DRAM cell capacitor leaks charge over time, the charge on each capacitor must be periodically refreshed. To prevent retention failure, the refresh interval should be less than the retention time. Since all memory cells do not have the same retention time because of process variations [1, 4, 17], the BER due to retention failure is given by

[TABLE]

where $t$ denotes a given refresh interval value. The random variable $T_{\text{retention}}$ represents the retention time of DRAM cells. It is clear that shorter refresh intervals decrease the BER due to retention failure. To guarantee data integrity, current DRAM standards conservatively employ the refresh interval of $64\text{\,}\mathrm{ms}$.

The refresh power $P$ is inversely proportional to the refresh interval as follows [6, 18]:

[TABLE]

where $C$ denotes the effective switching capacitance. This effective switching capacitance increases for higher-capacity DRAM devices. Hence, the refresh power consumption continues to increase as DRAM device capacity increases [4, 1, 18].

III DRAM Optimization Metrics

The refresh interval $t$ is a key parameter to control the trade-off between refresh power and fidelity. If we separate the data for each bit position in different subarrays by interleaving as in [11, 15, 19], then the corresponding refresh interval assignment is represented by a vector $\mathbf{t}=(t_{0},\ldots,t_{B-1})$ as shown in Fig. 2. Note that $t_{0}$ and $t_{B-1}$ represent the refresh intervals corresponding to least significant bit (LSB) and most significant bit (MSB), respectively. Subarrays can correspond to memory banks or memory chips depending on architecture configuration. Due to the current DRAM’s multi-chip and multi-bank architecture in Fig. 1, we can allocate different refresh intervals to each subarray with minimal hardware overhead [4, 6, 11].

In the following subsections, we describe the resource and fidelity metrics with the refresh interval assignment.

III-A Resource Metric: Refresh Power

From (2), the normalized refresh power for a $B$-bit word is given by

[TABLE]

Remark 1

The refresh power $\mathsf{P}(\mathbf{t})$ is a convex function of $\mathbf{t}$ because $t_{b}>0$ for $b\in[0,B-1]$.

III-B Fidelity Metrics: BER and MSE

Suppose that $p_{b}$ denotes the BER of the $b$th bit position. Since $p_{b}$ is a function of refresh interval $t_{b}$, we set

[TABLE]

for $b\in[0,B-1]$.

In many signal processing and ML tasks, the impact of bit errors depends on the bit position. For example, errors in the MSB position of image pixels degrade overall image quality much more than errors in the LSB position. Likely, an MSB error can cause a catastrophic loss in the inference accuracy of ML applications [15]. Hence, we use the MSE as a fidelity metric instead of the BER.

The MSE of $B$-bit words is given by

[TABLE]

where the weight $4^{b}$ represents the differential importance of each bit position [20, 15].

Remark 2

$\mathsf{MSE}(\mathbf{t})$* is convex if $g(\cdot)$ is convex. It is because a nonnegative weighted sum of convex functions is convex.*

It was reported that the BER increases exponentially with the refresh interval [5, 6, 21, 11]. Hence, we model the BER as

[TABLE]

where positive values of $\alpha$ and $\beta$ depend on the memory fabrication parameters.

Remark 3

$\mathsf{MSE}(\mathbf{t})$* is convex if $g(\cdot)$ is an exponential function as in (6).*

Table I summarizes the resource and fidelity metrics for single-bit and $B$-bit word. We note that these metrics are convex.

IV Formulation of Optimization Problems

IV-A Convex Optimization Problem

We formulate a convex optimization problem to determine the optimal refresh intervals. For a given refresh power constraint, we seek to minimize MSE as follows:

[TABLE]

where $\mathcal{P}$ is a constant corresponding to the given refresh power budget. Note that $\delta>0$ denotes the conservative minimum refresh interval, which in particular prevents $t_{b}=0$ (i.e., infinite refresh power). We set $\delta=0.064$ based on current DRAM standards.

Because of Remark 1 and Remark 3, the optimization problem (LABEL:eq:min_mse) is convex. Hence, we can obtain the global optimal solutions by standard convex programming algorithms. In addition, we can derive the optimal solution based on KKT conditions.

Theorem 4

The optimal refresh-interval vector $\mathbf{t}^{*}$ of (LABEL:eq:min_mse) is given by

[TABLE]

where $\nu$ is a dual variable of KKT conditions. Note that $\nu$ depends on the refresh power budget $\mathcal{P}$ for the given $\alpha$ and $\beta$. We can find $\nu$ efficiently by the bisection method as in [22]. Also, $W(\cdot)$ denotes the Lambert W function, which is the inverse function of $f(x)=xe^{x}$ [23].

Proof:

We define the Lagrangian $L_{1}(\mathbf{t},\nu,\mathbf{\lambda})$ associated with problem (LABEL:eq:min_mse) as

[TABLE]

where $\nu$ and $\mathbf{\lambda}=(\lambda_{0},\ldots,\lambda_{B-1})$ are the dual variables. The optimal solution is derived from $L_{1}$ and the corresponding KKT conditions. The details of the proof are given in Appendix A. ∎

The optimal refresh interval (8) can be interpreted by Fig. 3. As shown in Appendix A, the condition of $\frac{\nu}{4^{b}}=\alpha\beta t_{b}^{2}\exp(\beta t_{b})$ should be satisfied for any $t_{b}>\delta$ (i.e., $\frac{\nu}{4^{b}}>\alpha\beta\delta^{2}\exp(\beta\delta)$). If $\frac{\nu}{4^{b}}<\alpha\beta\delta^{2}\exp(\beta\delta)$, then the corresponding refresh interval is forced to $t_{b}=\delta$. As the refresh power budget $\mathcal{P}$ decreases, the dual variable $\nu$ is increased to allocate longer refresh intervals. If more refresh power is available, then $\nu$ is lower and the corresponding refresh intervals are reduced as shown in Fig. 3.

Note that $\mathbf{t}_{0}=(\delta,\ldots,\delta)$ corresponds to the maximum refresh power and the minimum MSE as follows.

Remark 5** (Maximum Refresh Power)**

The maximum refresh power is given by

[TABLE]

If $B=8$ and $\delta=0.064$, then $\mathsf{P_{max}}=125$.

Remark 6** (Minimum MSE)**

The minimum MSE is

[TABLE]

which is obtained by the maximum refresh power. Note that the MSE increases exponentially with the refresh interval $\delta$.

IV-B Discrete Refresh Intervals

In the previous subsection, we formulated the convex optimization problem by assuming that any real values can be assigned to refresh intervals. Here, we investigate the discrete-valued refresh interval optimization. If the optimized discrete refresh intervals are multiples of $\delta$ (e.g., $64\text{\,}\mathrm{ms}$), then the proposed optimization technique is compatible with current DRAM products. The reason is that any multiple of $\delta$ can be set as a refresh interval by gating the refresh commands [3, 4].

Suppose that $t_{b}=\Delta\cdot z_{b}$ where $\Delta=\gamma\delta$ and $z_{b}\in\mathbb{N}$ ($\mathbb{N}$ denotes the positive integers) for $b\in[0,B-1]$. Note that the step size of the refresh interval $\Delta$ is determined by $\gamma\in\mathbb{N}$, which controls the discrete optimization complexity and accuracy. Then, the convex optimization problem (LABEL:eq:min_mse) can be modified into the following convex integer programming problem:

[TABLE]

where the positive integer solution $\mathbf{z}^{*}$ results in the optimized discrete refresh interval by $\widetilde{\mathbf{t}}^{*}=\Delta\cdot\mathbf{z}^{*}$.

Although convex integer programming is NP-hard, it can be solved much more efficiently than general integer non-linear programming problems [24, 25]. We obtained the optimized discrete solutions by standard mixed-integer non-linear program (MINLP) solvers. The numerical results are provided in Section V.

V Numerical Results

We evaluate the solutions of convex optimization problem (LABEL:eq:min_mse) and the discrete optimization problem (LABEL:eq:min_mse_discrete). First, we estimate the parameters $\alpha$ and $\beta$ of (6). From the measured data in [21], we obtained the estimates of $\alpha=2.7737\times 10^{-7}$ and $\beta=1.9508$ (see Fig. 4). Note that these parameters depend on manufacturers, products, and temperature as shown in [5, Fig. 4]. We note that higher-capacity, later-generation DRAM devices suffer from more retention failures [17, 5].

Fig. 5 shows numerical results by solving (LABEL:eq:min_mse). Fig. 5LABEL:sub@fig:optimal_mse compares the MSEs of uniform refresh intervals and the optimal refresh intervals. At $\mathsf{MSE}=1$, the optimal refresh intervals reduce the refresh power consumption by $27\text{\,}\%$. For lower MSE, we can save more refresh power (e.g., $36\text{\,}\%$ refresh power reduction at $\mathsf{MSE}=10^{-1}$).

Fig. 5LABEL:sub@fig:optimal_psnr compares the peak signal-to-noise ratios (PSNRs) of refresh interval assignments, which is a widely used fidelity metric for image and video quality. The PSNR depends on the MSE as

[TABLE]

At $\mathsf{PSNR}=$50\text{,}\mathrm{d}\mathrm{B}, the optimized refresh intervals can reduce the refresh power by $29\text{\,}\%$. Further, the optimized refresh intervals achieve $38\text{\,}\%$ power reduction at $\mathsf{PSNR}=$60\text{\,}\mathrm{d}\mathrm{B}. The improvement by the optimized refresh intervals increases for a higher fidelity requirement. If we achieve a target fidelity (e.g., $\mathsf{PSNR}=$50\text{,}\mathrm{d}\mathrm{B} is a quite reliable value in real-world images [[26](#bib.bib26)]), we do not need to waste power by refreshing every $64\text{\,}\mathrm{ms}$, which requires $\mathsf{P_{max}}=125$ (see Remark [5](#Thmtheorem5)). Note that the optimized refresh interval assignment achieves $\mathsf{PSNR}=$50\text{\,}\mathrm{d}\mathrm{B} with $\mathsf{P}(\mathbf{t}^{*})=2.4$, which is less than $2\text{\,}\%$ of $\mathsf{P_{max}}$.

Fig. 6 shows the optimal refresh interval assignments by Theorem 4. The shorter refresh intervals (i.e., more refresh power assignments) are allocated to the more significant bits to minimize the MSE. As the refresh power budget $\mathcal{P}$ in (LABEL:eq:min_mse) increases, the refresh intervals for more significant bits converge to $\delta$. Fig. 6 shows that $t_{7}=\delta$ from $\mathcal{P}=36$. More refresh intervals become $\delta$ for higher refresh power budget.

Fig. 7 shows the MSEs obtained by solving convex integer programming problem (LABEL:eq:min_mse_discrete). This convex integer problem was solved by using Bonmin [25]. We observe that the MSE penalty due to discrete refresh intervals is negligible for a moderate step size $\Delta=\gamma\delta$. The MSE by discrete refresh intervals with $\Delta=\delta$ is almost the same as the optimal MSE. For $\Delta=15\delta$, the MSEs are distinct from the optimal MSEs from $\mathsf{P}=6$. Note that the maximum refresh power with $\Delta=15\delta$ is $\mathsf{P}=\frac{B}{15\delta}\simeq 8.33$.

VI Conclusion

We developed a principled approach to optimizing refresh intervals for energy-efficient memories. By formulating the convex optimization problem, we obtained the optimal refresh intervals to minimize the MSE under a refresh power budget. Also, we formulated a discrete optimization problem by taking into account the current DRAM standards and hardware implementation. The numerical results show that the optimum refresh intervals can achieve refresh power reductions of $29\text{\,}\%$ (at $\mathsf{PSNR}=$50\text{,}\mathrm{d}\mathrm{B}) and $38\text{\,}\%$ (at $\mathsf{PSNR}=$60\text{\,}\mathrm{d}\mathrm{B}), respectively.

Appendix A Proof of Theorem 4

The KKT conditions of (LABEL:eq:min_mse) are as follows:

[TABLE]

for $b\in[0,B-1]$. From (16), $\lambda_{b}$ is given by

[TABLE]

From (15) and (17),

[TABLE]

Suppose that $\nu=0$. Then $\lambda_{b}=4^{b}\alpha\beta\exp(\beta t_{b})\neq 0$. Hence, $t_{b}=\delta$ for any $b\in[0,B-1]$. This is a trivial solution and the corresponding refresh power is $\mathsf{P}((\delta,\ldots,\delta))=\frac{B}{\delta}$. If this trivial solution does not violate the power budget constraint (i.e., $\frac{B}{\delta}\leq\mathcal{P}$), then it will achieve the minimum MSE. However, we are more interested in the case of $\frac{B}{\delta}>\mathcal{P}$. Hence, we focus on $\nu\neq 0$, which results in $\sum_{b=0}^{B-1}{\frac{1}{t_{b}}}=\mathcal{P}$.

If $\lambda_{b}>0$, then $t_{b}=\delta$. By (16), the condition of $\lambda_{b}>0$ is equivalent to $\frac{\nu}{4^{b}}<\alpha\beta t_{b}^{2}\exp{(\beta t_{b})}$. By (18), we claim that $t_{b}^{*}=\delta$ for $\frac{\nu}{4^{b}}<\alpha\beta\delta^{2}\exp{(\beta\delta)}$. If $\lambda_{b}=0$, then

[TABLE]

which is equivalent to $\frac{\beta t_{b}}{2}\exp{\left(\frac{\beta t_{b}}{2}\right)}=\frac{\beta}{2}\sqrt{\frac{\nu}{4^{b}\alpha\beta}}$. By setting $x=\frac{\beta t_{b}}{2}$, we obtain $x\exp{(x)}=\frac{\beta}{2}\sqrt{\frac{\nu}{4^{b}\alpha\beta}}$. Hence, $W\left(\frac{\beta}{2}\sqrt{\frac{\nu}{4^{b}\alpha\beta}}\right)=x=\frac{\beta t_{b}}{2}$, i.e., $t_{b}=\frac{2}{\beta}W\left(\frac{\beta}{2}\sqrt{\frac{\nu}{4^{b}\alpha\beta}}\right)$.