# On the Optimal Refresh Power Allocation for Energy-Efficient Memories

## TL;DR

This paper introduces an optimization framework for allocating refresh power in DRAM to minimize error while reducing power consumption, especially beneficial for high-capacity and mobile memory devices.

## Contribution

It formulates a convex optimization model for optimal refresh power allocation and an integer programming approach for discrete refresh intervals, achieving significant power savings.

## Key findings

- Optimized refresh intervals reduce power by 29% at 50dB SNR.
- The convex model guarantees optimal power allocation under error constraints.
- Numerical results demonstrate improved energy efficiency in DRAM.

## Abstract

Refresh is an important operation to prevent loss of data in dynamic random-access memory (DRAM). However, frequent refresh operations incur considerable power consumption and degrade system performance. Refresh power cost is especially significant in high-capacity memory devices and battery-powered edge/mobile applications. In this paper, we propose a principled approach to optimizing the refresh power allocation. Given a model for the bit error rate dependence on power, we formulate a convex optimization problem to minimize the word mean squared error for a refresh power constraint; hence we can guarantee the optimality of the obtained refresh power allocations. In addition, we provide an integer programming problem to optimize the discrete refresh interval assignments. For an 8-bit accessed word, numerical results show that the optimized nonuniform refresh intervals reduce the refresh power by 29% at a peak signal-to-noise ratio of 50dB compared to the uniform assignment.