Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption

TL;DR

This study uses simulations to evaluate thin ferroelectric FDSOI NCFETs, demonstrating significant power savings and improved performance over traditional FDSOI MOSFETs in high-frequency digital circuits.

Contribution

It provides a comparative analysis of HfO2 and PZT ferroelectric materials in FDSOI NCFETs, highlighting their advantages for low-power high-performance digital circuits.

Findings

HfO2 FDSOI NCFETs reduce power consumption by ~66% compared to baseline.

PZT FDSOI NCFETs reduce power consumption by ~86% for similar performance.

Power-delay product is ~24% lower with HfO2 and ~21% lower with PZT NCFETs.

Abstract

The paper presents simulation study of thin ferroelectrics (Si doped HfO2, PZT) PGP FDSOI NCFETs at circuit level for high performance, low VDD low-power digital circuits. The baseline PGP FDSOI MOSFET has 20 nm metal gate length with supply voltage varying from 0.5 V to 0.9 V. The circuits studied were 3-stage CMOS ring oscillator, NAND-2 and NOR-2 gates at a frequency of 20 GHz. The paper shows that HfO2 FDSOI NCFET based NAND-2 gates can provide significant reduction in average power consumption, which was ~66% that of baseline FDSOI MOSFET based NAND-2 gates for comparable performance. For the same performance, the average power consumption for PZT FDSOI NCFET based NAND-2 gate was ~86% that of baseline FDSOI MOSFET based NAND-2 gate. The power-delay product of HfO2 FDSOI NCFET based gates was found to be ~24% lower than baseline FDSOI MOSFET based gates and that of PZT FDSOI NCFET based gates was found to be ~21% less than that of baseline FDSOI MOSFET based gates. The performance of HfO2 FDSOI NCFET based gates with increased fan-in and fan-out was also found to be superior to PZT FDSOI NCFET based gates and baseline FDSOI MOSFET based gates.

Tables

Table 1. TABLE I: Performance of 3-stage ring oscillators, ∣ ∣ \mid V BS ∣ ∣ \mid =1 V.

VDD (V)	fosc,BL (GHz)	fosc,PZT (GHz)	f${}_{osc,Hf{O}_2}$ (GHz)
0.5	21	53	67
0.6	46	84	101
0.7	73	113	126
0.8	99	140	151
0.9	120	162	171

Table 2. TABLE II: Propagation delay and average power consumption for NAND-2 gates using FDSOI NCFETs and baseline devices. The signal frequency is 20 GHz, ∣ ∣ \mid V BS ∣ ∣ \mid =1 V.

VDD	${\tau }_{p,BL}$	${\tau }_{p,PZT}$	${\tau }_{p,Hf{O}_2}$	Pavg,BL	Pavg,PZT	P${}_{avg,Hf{O}_2}$
(V)	(ps)	ps	(ps)	($\mu$W)	($\mu$W)	($\mu$W)
0.5	7.05	3	2.45	8.86	10.75	11.74
0.6	3.3	1.97	1.75	13	15.38	16.82
0.7	2.15	1.54	1.46	17.69	20.8	22.65
0.8	1.67	1.33	1.28	23	26.98	29.32
0.9	1.41	1.18	1.17	29	33.99	37.06

Table 3. TABLE III: Propagation delay and average power consumption for NOR-2 gates using FDSOI NCFETs and baseline devices. The signal frequency is 20 GHz, ∣ ∣ \mid V BS ∣ ∣ \mid =1 V.

VDD	${\tau }_{p,BL}$	${\tau }_{p,PZT}$	${\tau }_{p,Hf{O}_2}$	Pavg,BL	Pavg,PZT	P${}_{avg,Hf{O}_2}$
(V)	(ps)	ps	(ps)	($\mu$W)	($\mu$W)	($\mu$W)
0.5	-	3.55	2.96	-	10.68	11.63
0.6	3.8	2.3	2.08	13	15.18	16.52
0.7	2.5	1.77	1.68	17.7	20.46	22.27
0.8	1.9	1.5	1.46	23	26.47	28.8
0.9	1.6	1.33	1.32	29	33.26	36.24

Table 4. TABLE IV: Propagation delay and average power consumption for NAND-2 gates using HfO 2 FDSOI NCFETs for different T FE . The signal frequency is 20 GHz, ∣ ∣ \mid V BS ∣ ∣ \mid =1 V.

VDD	${\tau }_p$	${\tau }_p$	${\tau }_p$	${\tau }_p$	Pavg	Pavg	Pavg	Pavg
	(BL)	(HfO2)	(HfO2)	(HfO2)	(BL)	(HfO2)	(HfO2)	(HfO2)
		(5 nm)	(10 nm)	(15 nm)		(5 nm)	(10 nm)	(15 nm)
(V)	(ps)	(ps)	(ps)	(ps)	($\mu$W)	($\mu$W)	($\mu$W)	($\mu$W)
0.5	7.05	3.85	2.45	1.8	8.86	10.24	11.74	13.86
0.6	3.3	2.31	1.75	1.46	13	14.63	16.82	19.69
0.7	2.15	1.75	1.46	1.27	17.69	19.82	22.65	26.56
0.8	1.67	1.44	1.28	1.18	23	25.72	29.32	34.38
0.9	1.41	1.27	1.17	1.13	29	32.1	37.06	40.1

Full text

I Introduction

As the technology continues to scale down, the use of ferroelectrics in MOSFETs to provide negative capacitance (NC) effect holds significance in achieving sub-60 mV/decade subthreshold swing (SS) [1]. The benefits of using NCFETs for low-power operation have been highlighted in several studies for different ferroelectrics, viz., PZT [2, 3, 4, 5, 6], BTO [2] and doped HfO2 (Si, Zr, Y, Gd, La) [7, 8, 9, 10]. The ferroelectrics of greatest interest are PZT and doped HfO2 (Si, Zr). The use of doped HfO2 as a ferroelectric in NCFETs is attractive not only because it is compatibile with existing fabrication techniques, but also for its high switching speed [11]. Henceforth, Si doped HfO2 used as ferroelectric in this work is referred to as HfO2. Recent studies have also reported fabrication of NCFETs using standard gate-last process [12, 13]. Although several studies have been reported on these ferroelectrics, to the best of our knowledge, a comprehensive study of HfO2 FDSOI NCFETs and PZT FDSOI NCFETs at the gate level for 20 nm gate length has not been reported. In this paper, a detailed study of performance and average power consumption of FDSOI NCFETs with a thin layer of HfO2 or PZT in the gate stack is reported for logic circuits. The baseline FDSOI MOSFET based gates are operated at low VDD to save power. But, this causes performance degradation. The solution to this problem is using FDSOI NCFETs at low VDD for logic gates which achieve high performance at low average power consumption. The FDSOI NCFETs have been used to build 3-stage CMOS ring oscillators and 2-input universal gates, namely, NAND and NOR. A comparison has been drawn with the performance of the same circuits made using baseline FDSOI MOSFETs. Further, Power-Delay Product (PDP) of FDSOI NCFET based gates has been evaluated and compared with that of FDSOI MOSFET based gates. The damping effect of the ferroelectrics is ignored in this work for prediction of best device performances [14],[15].

This paper is organized as follows. In Section II the device details are given, Section III covers evaluation of FDSOI NCFET based logic gates, Section IV compares the performance of HfO2 FDSOI NCFET based gates with PZT FDSOI NCFET based gates followed by conclusion in Section V.

II Device Details

FDSOI MOSFETs with Partial Ground Planes (PGPs) were used as baseline devices as PGPs are known to improve Drain Induced Barrier Lowering (DIBL) behaviour as explained in subsequent subsection B. The structure of baseline FDSOI MOSFET is shown in Fig. 1. The devices had a metal gate length of 20 nm and a HKMG gate stack with an EOT of 0.9 nm. The silicon layer that forms the channel was 5 nm thick and was intrinsically doped ($\sim$1015 cm*-3*). The BOX was 10 nm thick. The source and drain regions were degenerately doped with a doping concentration of $\sim$1020 cm*-3*. The PGPs were heavily doped ($\sim$1020 cm*-3*) regions located 6 nm from the source/channel and drain/channel junctions and had the same dimensions as in [16]. FDSOI NCFETs studied in this paper had a Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) structure, as shown in Fig. 1. The internal metal layer in the MFMIS structure helps in providing a uniform electric field to the underlying baseline device, ignoring charge trapping or detrapping [17],[18].

II-A Baseline device

To realize the baseline device, a structure as proposed in [19] was first simulated at 20 nm gate length in Silvaco ATLAS TCAD [20]. The mobility models used were Lombardi mobility model and high field mobility model. Fermi-Dirac statistics, Auger and Shockley-Read-Hall recombination models were also invoked. Since the silicon thickness was 6 nm, quantum confinement effect was also considered. The BOX thickness was 25 nm as proposed in [19]. After calibration with [19], the thicknesses of the silicon layer and BOX were reduced to 5 nm and 10 nm respectively and PGPs were introduced as per [16]. A constant reverse bias of $\mid$1 V$\mid$ was applied to achieve better front gate control [21]. The threshold voltage was determined based on the constant current method, at a drain current of 100 $\mu$A/$\mu$m. The threshold voltage of baseline FDSOI n-MOSFET was 0.5 V and that of baseline FDSOI p-MOSFET was -0.5 V. The output characteristics of the baseline FDSOI n-MOSFET and FDSOI p-MOSFET are shown in Fig. 2.

II-B Role of PGPs

PGPs have been reported to cause a reduction in DIBL as they help in keeping the gate-induced field high in the silicon layer of an SOI MOSFET [16, 22, 23]. Fig. 3 shows $\sim$12.35% reduction in DIBL (from 178 mV/V to 156 mV/V) achieved after incorporation of PGPs in baseline FDSOI n-MOSFETs. Fig. 3 shows $\sim$13.5% reduction in DIBL from 333 mV/V to 288 mV/V, due to PGPs in baseline FDSOI p-MOSFETs. The effect of PGPs in FDSOI n-NCFETs was also analysed and it was found that the reduction in DIBL in FDSOI n-NCFETs was $\sim$33% (from 35.3 mV/V to 23.5 mV/V). The PGPs can be self-aligned with the gate as described in [24, 25, 22].

II-C Realization of PGP FDSOI NCFET

The 2-D electrostatics obtained from TCAD were solved self consistently with Landau-Khalatnikov equation in MATLAB to simulate a PGP FDSOI NCFET [5]. The Landau coefficients of HfO2 ($\alpha$ = -3.9e10 cm/F, $\beta$ = 1.0e20 cm5/F/C2, $\gamma$ = -2.65e28 cm9/F/C4) were obtained from [7] and those of PZT ($\alpha$ = -13.5e9 cm/F, $\beta$ = 3.05e18 cm5/F/C2, $\gamma$ = -2.11e25 cm9/F/C4) were obtained from [5]. FDSOI NCFETs used in our study with HfO2 had a ferroelectric thickness (TFE) of 10 nm. Even though a TFE of 20 nm for HfO2 did not show hysteresis in DC simulations, as shown in Fig. 4, hysteresis was observed at the circuit level for this TFE. This is consistent with the behaviour reported in [26]. Similarly, as shown in Fig. 5, FDSOI NCFETs with a TFE of 30 nm for PZT did not show hysteresis in DC simulations. But hysteretic behaviour was observed for this value of TFE of PZT at the circuit level. Using constant current method, at a drain current of 100 $\mu$A/$\mu$m, the threshold voltage of HfO2 FDSOI NCFETs (TFE=10 nm) was 0.34 V (n-type) and -0.3 V (p-type). Similarly, the threshold voltage of PZT FDSOI NCFETs (TFE = 20 nm) was 0.43 V (n-type) and -0.42 V (p-type). The output characteristics of HfO2 FDSOI NCFETs (TFE = 10 nm) are shown in Fig. 6 and the output characteristics of PZT FDSOI NCFETs (TFE = 20 nm) are shown in Fig. 7. The negative DIBL behaviour at high VGS,TOP in FDSOI p-NCFET is smaller than in FDSOI n-NCFET and is consistent with the observation and explanation provided in [15]. The increased thickness of PZT in comparison to HfO2 is consistent with our reported study based on $\alpha$, $\beta$, $\gamma$ coefficients which showed that HfO2 ferroelectric is expected to give greater non-hysteretic gain in comparison to PZT for given TFE[27].

III Evaluation of Logic Gates using NCFETs

Two of the most popular ferroelectrics, HfO2 and PZT have been used to study FDSOI NCFETs for digital circuits. The circuits studied were 3-stage CMOS ring oscillator, NAND-2 with fan-out of 1 and NOR-2 with fan-out of 1 [28]. The circuits were simulated in Synopsys HSPICE using a look-up table approach [29]. The circuits with FDSOI NCFETs were studied at a supply voltage (VDD) of 0.5 V which is also the threshold voltage of baseline FDSOI MOSFETs. Further, the comparison of FDSOI NCFETs with baseline FDSOI MOSFETs was also drawn at VDD ranging from 0.5 V to 0.9 V. The propagation delay, $\tau_{p}$ was based on the charge-current relationship [30].

In this study, the p-type devices were not scaled and in case of both baseline FDSOI MOSFETs and FDSOI NCFETs, the n-type and p-type devices had the same dimensions. The load capacitance (Cload) at the output of each inverter in the ring oscillator was taken as the sum of output capacitance of the previous stage and the input capacitance of the next stage. To obtain gate delay, a model assumption was made that the intrinsic capacitance, Cint, of the logic gate scales with the gate capacitance of the device (CG), i.e., Cint $\simeq$ CG. The external capacitance (Cext) in case of the baseline device was taken as the input capacitance of the inverter that loads the gate, which is, Cext = CGS,n + CGS,p + CGD,n(1-AV) + CGD,p(1-AV), as shown in Figs. 8 and 9. A similar expression was dervied for the case of FDSOI NCFETs taking the ferroelectric capacitance, CFE into account. The capacitances CGS,n, CGS,p, CGD,n and CGD,p for the baseline device were obtained from TCAD and CFE was calculated as CFE $\approx$ 1/(2$\alpha$TFE) as outlined in [31]. Here, AV is the gain of the inverter (=-1). For case of both baseline FDSOI MOSFETs and FDSOI NCFETs based gates, Cext is approximately equal to CG. For logic gate, Cload = CG + Cext. The input capacitance of the gate (Cin) was 2CG. Therefore, for a fan-out of 1, Cload/Cin $\simeq$ 1, is verified. The capacitance C1 = CDB + CSB + CGD(1-AV). Miller effect was considered in our analysis. Worst-case input patterns were considered for obtaining gate delays. For NAND-2 gate, the worst case input pattern was taken as A=1, B=0$\rightarrow$1 for $\tau_{p,HL}$ and A=1, B=1$\rightarrow$0 for $\tau_{p,LH}$. Similarly, for NOR-2, the worst case input pattern for $\tau_{p,HL}$ was taken as A=0$\rightarrow$1, B=0 and A=1$\rightarrow$0, B=0 for $\tau_{p,LH}$.

The results obtained for frequency of oscillation (fosc) of ring oscillators are shown in Table I. For baseline FDSOI MOSFET based ring oscillator, * fosc* at VDD of 0.5 V was 21 GHz while HfO2 FDSOI NCFET based ring oscillator had * fosc* of 67 GHz at the same VDD, as shown in Fig. 10. PZT FDSOI NCFET based ring oscillator had fosc of 53 GHz which was greater than in case of the baseline device based ring oscillator but less than that of HfO2 FDSOI NCFET based ring oscillator. For analyzing the performance and average power consumption of the logic gates, the input signal frequency was varied from 5 KHz to 20 GHz, which is consistent with results in Table I.

The results obtained for performance and average power consumption for NAND-2 gates with fan-out of 1 are shown in Tabel II at different VDD. It can be clearly seen that for comparable performance at 20 GHz of baseline FDSOI MOSFET based NAND-2 gate (VDD = 0.7 V), PZT FDSOI NCFET based NAND-2 gate (VDD = 0.6 V) and HfO2 FDSOI NCFET based NAND-2 gate (VDD = 0.5 V), the average power consumption is least in HfO2 FDSOI NCFET based NAND-2 gate. For HfO2 FDSOI NCFET based NAND-2 gate, the average power consumption was $\sim$66% and for PZT FDSOI NCFET based NAND-2 gate it was $\sim$86% that of baseline FDSOI MOSFET based NAND-2 gate. This holds true for other VDD values also as shown in Table II. This finding is consistent with the analysis reported in [32]. Figure 11 shows the variation of propagation delay and average power consumption of NAND-2 gate for all cases at different VDD.

Table III shows the results obtained for performance and average power consumption for NOR-2 gates. The baseline FDSOI MOSFET based NOR-2 gates could not be operated beyond 10 GHz at a VDD of 0.5 V. At comparable performance of $\sim$2 ps at 20 GHz, the average power consumption of HfO2 FDSOI NCFET based NOR-2 gate was $\sim$72% and for PZT FDSOI NCFET based NOR-2 gate it was $\sim$88% that of baseline FDSOI MOSFET based NOR-2 gate. The improved performance with reduced power consumption for HfO2 FDSOI NCFETs based NOR-2 gate is shown in Fig. 12.

III-A Power-Delay Product

Power-Delay Product (PDP) is an important metric for digital circuits and gives an estimate of the amount of energy consumed in an operation. The reduction in PDP of FDSOI NCFETs based NAND-2 gates over those with FDSOI MOSFET based NAND-2 gates is shown in Figs. 13 and 14 for HfO2 and PZT ferroelectrics, respectively, at signal frequency of 20 GHz. For a comparable propagation delay of $\sim$2 ps, HfO2 FDSOI NCFET based NAND-2 gates had a PDP of $\sim$29 $\mu$W.ps (VDD = 0.5 V), PZT FDSOI NCFET based NAND-2 gates had a PDP of $\sim$30.3 $\mu$W.ps (VDD = 0.6 V) while baseline FDSOI MOSFET based NAND-2 gates had a PDP of $\sim$38 $\mu$W.ps (VDD = 0.7 V).

The PDP results for HfO2 FDSOI NCFET based NOR-2 gate are shown in Fig. 15 and for PZT FDSOI NCFET based NOR-2 gate the results are shown in Fig. 16. The PDP in case of baseline FDSOI MOSFET based NOR-2 gates for a propagation delay of $\sim$2 ps at 20 GHz, was nearly $\sim$43 $\mu$W.ps at VDD of 0.8 V. For the same delay, the PDP of PZT FDSOI NCFET based NOR-2 gate was $\sim$36 $\mu$W.ps at a VDD of 0.7 V and PDP for HfO2 FDSOI NCFET based NOR-2 gate was $\sim$34.3 $\mu$W.ps at a VDD of 0.6 V. The PDP results clearly highlight the significance of the thin ($\sim$10 nm) layer of HfO2 ferroelectric in FDSOI NCFETs for digital circuit design. The analysis shows that thin layers of ferroelectrics in FDSOI NCFETs help in the improvement of device performance for digital circuit applications.

III-B Effect of fan-in and fan-out

The effect of increased fan-in and fan-out of logic gates on performance and average power consumption was also studied. Due to increased current driving capability of FDSOI NCFET devices, the performance of FDSOI NCFET based gates was found to be better with increased fan-in and fan-out. The fan-in was increased from 2 to 4 and 8 with a fan-out of 1. When fan-in was increased to 4 for NAND gates, at a VDD of 0.5 V, HfO2 and PZT FDSOI NCFET based NAND gates could be operated till 20 GHz. But, the FDSOI MOSFET based NAND-4 gate could not be operated beyond 5 GHz at the same operating voltage. Fig. 17 shows the comparison of performance and average power consumption for NAND-4 gates at different VDD values. Further, HfO2 FDSOI NCFET based NAND gates continued to have superior performance when fan-in was increased to 8. While at a VDD of 0.5 V, the baseline FDSOI MOSFET based NAND-8 gates could not be operated beyond 1 GHz, the HfO2 and PZT FDSOI NCFET based NAND-8 gates could operate till 10 GHz. Similar results were obtained when fan-in of NOR gates was increased to 4 and 8. The results for NOR-4 gates are shown in Fig. 18.

The fan-out of NAND-2 and NOR-2 gates was increased to 2 and performance and average power consumption of the gates were analyzed as shown in Figs. 19 and 20. While at a VDD of 0.5 V, HfO2 and PZT FDSOI NCFET based NAND-2 gates driving 2 inverters could be operated till 20 GHz, the baseline FDSOI MOSFET based NAND-2 gate driving 2 CMOS inverters could not be operated beyond 10 GHz. Similarly, when NOR-2 gates driving 2 inverters using baseline FDSOI MOSFETs were operated at 0.5 V of VDD, they could not function beyond 5 GHz. On the other hand PZT FDSOI NCFET based NOR-2 gates with fan-out of 2 could not operate beyond 10 GHz while HfO2 FDSOI NCFET based NOR-2 gates with fan-out of 2 could be operated till 20 GHz at a VDD of 0.5 V.

III-C Effect of change in TFE

The influence of change in TFE on improvement in delay and reduction in average power can be instructive from device design and device fabrication point of view. Table IV shows the performance of NAND-2 gates with fan-out of 1 for different TFE of HfO2. As TFE is increased, the delay improves for a given VDD but the average power consumption also increases. For the same delay of $\sim$1.4 ps, the average power consumption in the baseline FDSOI MOSFET based gate is $\sim$29 $\mu$W. It is reduced by $\sim$11% at TFE of 5 nm and by $\sim$32% at TFE of 15 nm. Similar results were obtained for NOR-2 gates also.

IV Comparison of HfO2 NCFETs and PZT NCFETs

As discussed in the preceding sections, HfO2 FDSOI NCFET based circuits show better performance than PZT FDSOI NCFET based circuits. This is despite the fact that for FDSOI NCFETs used in our study, TFE of PZT ($\sim$20 nm) was greater than TFE of HfO2 ($\sim$10 nm). For NAND-2 gates with fan-out of 1, HfO2 FDSOI NCFET based NAND-2 gates are 18% faster than PZT FDSOI NCFET based NAND-2 gates at the same VDD of 0.5 V. Similar results were obtained for NOR-2 gates also.

V Conclusion

The paper shows the significance of thin ($\sim$10 nm) HfO2 and ($\sim$20 nm) PZT as ferroelectrics in the gate stack of FDSOI NCFETs for high performance, low VDD low-power digital circuits at 20 nm gate length. The study of HfO2 FDSOI NCFET based gates and PZT FDSOI NCFET based gates shows that HfO2 as a ferroelectric is more promising for high performance, low VDD low-power digital circuits. Further, significant improvement is achieved in the power-delay product by using HfO2 FDSOI NCFETs for logic gates. The performance of HfO2 FDSOI NCFET based gates for increased fan-in and fan-out was also found to be superior to PZT FDSOI NCFET based gates and baseline FDSOI MOSFET based gates. However, the study did not consider the damping effect of ferroelectrics.