A high-performance MoS2 synaptic device with floating gate engineering for Neuromorphic Computing

TL;DR

This paper introduces a high-performance MoS2-based synaptic device with floating gate engineering that mimics biological synapses and demonstrates energy-efficient neuromorphic computing capabilities.

Contribution

It presents a novel MoS2 floating gate transistor with near-ideal subthreshold swing for neuromorphic applications, showcasing features like STDP and energy efficiency.

Findings

Achieved subthreshold swing of 77 mV/decade over four decades of current

Demonstrated spike time dependent plasticity (STDP) in the device

Showed energy-efficient operation suitable for neuromorphic systems

Abstract

As one of the most important members of the two dimensional chalcogenide family, molybdenum disulphide (MoS2) has played a fundamental role in the advancement of low dimensional electronic, optoelectronic and piezoelectric designs. Here, we demonstrate a new approach to solid state synaptic transistors using two dimensional MoS2 floating gate memories. By using an extended floating gate architecture which allows the device to be operated at near-ideal subthreshold swing of 77 mV/decade over four decades of drain current, we have realised a charge tunneling based synaptic memory with performance comparable to the state of the art in neuromorphic designs. The device successfully demonstrates various features of a biological synapse, including pulsed potentiation and relaxation of channel conductance, as well as spike time dependent plasticity (STDP). Our device returns excellent energy efficiency figures and provides a robust platform based on ultrathin two dimensional nanosheets for future neuromorphic applications.

Equations

$$I_{tunnel}(V)=\frac{A_{ch}{q}^{3}m{V}_{tunnel}^2}{8\pi h{\varphi }_b{d}^2{m}^{\ast }}\exp [\frac{-8\pi \sqrt{2m^{\ast }}{\varphi }_b^{\frac{3}{2}}d}{3hq{V}_{tunnel}}]$$

$$\Delta G\%=\frac{G_{final}-G_{initial}}{G_{initial}}\times 100\%$$

$$\Delta G\propto \{\begin{array}{ll}\exp (-\frac{\Delta t}{{\tau }_{+}}),& \text{if }\Delta t\ge 0\\ -\exp (\frac{\Delta t}{{\tau }_{-}}),& \text{if }\Delta t\le 0\end{array}$$

$$E=I_{sd}\times t_{pulse}\times V_{sd}$$

Full text

Understanding the complexities in the functioning of the human brain has been one of the foremost challenges in the field of neuroscience. Among the several proposed models, only a few can explain the operation of a human brain and that too for a very limited set of functionalities 1; 2; 3. From an electronic point of view, the computational architecture of a brain is vastly different from that of a traditional von Neumann architecture based system 4; 5. This has led to the emergence of neuromorphic computation schemes 6; 7; 8; 9; 10. Current computation follows an architecture where processing and storage of data is handled by separate entities whereas in neuromorphic computation, processing and storage of data is handled by a single element which acts as the electrical analogue of a synapse. Mimicing the functionality and density of synapses in the brain would lead to a massive reduction in energy consumption and immensely enhance computational capabilities like parallel processing. Given the high density of synapses required, traditional silicon based devices which are plagued by power dissipation and short channel effects are rendered unsuitable for scalable neuromorphic applications 11; 12. This makes ultrathin two dimensional materials a perfect candidate for the active element of a synaptic transistor given their immunity to short channel effects and excellent gate coupling at nanometer length scales 12; 13.

Biologically, a synapse functions by changing its conductivity based on the sequence of synaptic pulses it receives. This is accomplished by varying the concentration of neurotransmitters or chemical stimulants which control the conductivity of the junction between two neurons 14. An ideal synaptic transistor must possess the twin qualities of being a non-volatile memory while inculcating a learning based mechanism to deduce its conductance from the history of applied inputs 15; 16; 17; 18; 19; 20; 21; 22; 23; 24; 25; 26; 27; 28; 29; 30. A considerable amount of literature currently exists on transition metal oxide based synaptic devices in both two terminal memristor and three terminal transistor geometry 17; 20. However, oxides in general have a large band gap and require ionic liquid gating which diminishes the long term usability of these devices because of the short lifetime of most liquid gates. Furthermore, most of these devices utilise some form of electrochemical reaction to alter the concentration of an ionic species, and hence the channel conductance, making them very sensitive to environmental conditions like humidity, temperature etc. 20. The requirement of a liquid gate can be avoided by substituting the transition metal oxide with a chalcogenide like molybdenum disulphide (MoS2) because of its comparatively lower band gap and better coupling to metallic gates 12. MoS2 has already been used as an active element in high quality non-volatile memory cells with high ON/OFF ratio 31; 32; 33; 34 and appears to be a prime candidate for a complete solid state based synaptic transistor. It is a scalable semiconducting platform, with a layer dependent bandgap in the visible range 35; 36; 37, exhibits a respectable carrier mobility (1-30 cm2/Vs) and displays unique transport properties like variable range hopping, percolative switching and valleytronic effects 38; 39; 40; 41; 42; 43; 44; 45.

However, the current architecture of floating gate (FG) memory with MoS2 is not conducive for realistic neuromorphic applications as it needs large gate voltage pulses ($\sim$ 30 V) in three terminal geometry 31 while a large energy dissipation per pulse is observed when the device is operated in two terminal mode 46. In this paper, we have addressed this difficulty by adopting an extended FG device architecture for the MoS2 FET. Owing to its two-dimensional nature, MoS2 can be readily inserted in a planar floating gate (FG) architecture, where one or more metallic layers (the FGs) act as temporary storage of charge induced by a global back or top gate 31; 47; 46. FG memory devices have been deployed in MOS architecture for a considerable period of time, where the tunneling of charge between the channel and the FG enables storage of information 48; 49. With improvements in fabrication techniques for two dimensional systems, it is possible to create a two dimensional analogue of a FG memory by stacking different van der Waal layered materials on top of each other in an atomic lego or heterostructure 50. We incorporate this idea in our work and demonstrate the performance of a floating gate memory device with MoS2 as the active element. We have implemented an extended graphene FG in our devices enabling us to improve the gating efficiency which consequently leads to an almost ideal subthreshold swing and reduces the required drain bias and switching pulse for stable memory action. These benefits extend to neuromorphic applications leading to a reduction in the pulse heights required for long term potentiation and depression of the channel which reduces the stress on the gate dielectric while improving the integrability of the device with current neuromorphic systems. The FG and the channel are separated by a hexagonal boron nitride (hBN) tunnel barrier which controls the charge transfer between them, enabling us to tune the channel conductance. Distinct from previous reports of MoS2 based synaptic memtransistors, which utilized bias induced motion of defect states in CVD (chemical vapour deposition) grown thin films to demonstrate the effect 18, here we explore the possibility of controlled charge tunneling mediated multiple conductance states and synaptic activity in defect-free exfoliated MoS2 layers. Using an extended FG architecture, we demonstrate hysteretic switching at near ideal subthreshold swing (77 mV/dec) in a trilayer stack of MoS2, hBN and graphene. We establish quantitatively that the hysteresis is caused by charge tunneling through hBN, and exploit the same to emulate spike time dependent plasticity at energy dissipation below 0.3 pJ.

The experiments were performed on a heterostructure of mechanically exfoliated flakes of MoS2, hBN and single/few layer graphene placed on a conventional $p^{++}$-Si/(285 nm)SiO2 substrate (Figure 1(a)) (details of devices used provided in Supplementary Table S1). Individual layers were first exfoliated separately, searched under an optical microscope for suitable flakes using optical contrast and characterized by Raman spectroscopy for MoS2 and graphene (see Supplementary Figure S1). The thickness of the hBN flake ($\approx$ 5 nm - 7 nm) was obtained via AFM measurements (see Supplementary Figure S2). We fabricated the heterostructure (Figure 1(b)) using a dry transfer method in an optical microscope with precision rotation and translation stages which assisted in the alignment of the individual layers 51. Electrical contacts were defined using electron beam lithography followed by metallization via thermal evaporation of Cr(5 nm)/Au(50 nm). The extended FG was fabricated by lithographically connecting the graphene layer to a large area floating gold pad as shown in Figure 1(c). The use of hBN as the intermediate layer was prompted by its excellent dielectric properties in the single crystalline form and large band gap ($\sim$ 6 eV), which allows a controlled charge tunneling while reducing unintentional leakage of charge and providing a defect free substrate for the MoS2 channel 52; 53; 54; 55; 56. Extension of the floating gate increases the total area of the SiO2 capacitor ($\approx$ 45000 $\mu$m2, the area of the FG) which results in $C_{1}\gg C_{2}$ in Figure 1(c), where $C_{1}$ and $C_{2}$ are the SiO2 ($\approx$ 5.72 pF) and hBN ($\approx$ 5.9 fF) capacitance respectively. This increases the effective Si*++* - channel capacitance to that across the hBN layer only.

Figure 1(d) and (e) demonstrates the back gate transfer characteristics observed in the extended floating gate MoS2 synaptic transistors. The threshold voltage is lower for the forward sweep (solid line) and higher for the reverse sweep (dashed line) leading to an anti-hysteretic transport. Additionally, the hysteresis window is sweep range dependent. We see a continuous decrease in the hysteresis window size (defined by the difference between the threshold voltage for the reverse and forward sweep) from $\approx$ 11 V for the largest sweep range of $\approx$ 18 V (Figure 1(e)) to a hysteresis-free transport for sweep ranges below $\approx$ 6 V (Figure 1(e)). From Figure 1(d), we observe that the entire hysteresis window can be located at any chosen range of gate bias by changing the center of the back gate sweep range. The top and bottom panel in Figure 1(d) show hysteresis windows centered about a negative and positive gate bias, respectively, with one centered about zero gate bias depicted in Figure 1(e). Hence, we see hysteresis even when the back gate voltage is either positive, negative or changing between positive and negative values during the sweep (Figure 1(d),(e)). This is important since a control over the threshold voltage is an essential component in designing a power efficient FET 57; 58; 59. Figure 1(f) compares the subthreshold slope for five devices with varying configurations of the FG. Devices with an extended FG (D1, D2 and D3) demonstrate an almost ideal subthreshold slope of $\approx$ 80 mV/decade which increases to $\approx$ 300 mV/decade on removing the extension of the FG (D9) while devices with no FG (D10) operate at an even larger subthreshold slope of $\approx$ 1000 mV/decade. Capacitance engineering via extension of the FG leads to faster ON/OFF transitions with improved energy efficiency, both of which are of considerable importance in neuromorphic applications (Supplementary section II).

To explain the hysteresis in these devices, we postulate a charge trapping mechanism as shown in Figure 1(g). Starting from an initial flatband condition at zero back gate bias, $i.e.$ $V_{g}$= 0 V, we increase $V_{g}$ leading to an electron doping in MoS2. Some electrons tunnel through the hBN into graphene (indicated by black arrow pointing in the direction of charge transfer in Figure 1(g) (panel II)) leading to a screening of the gate voltage as indicated in panel II. On decreasing the gate bias, this screening enables us to attain the flatband condition or OFF state at a value of $V_{g}>$ 0 V (panel III of Figure 1(g)). Further decreasing the gate bias leads to a tunneling of electrons from graphene to the MoS2 layer (or equivalently holes from the MoS2 to graphene layer) (panel IV and V of Figure 1(g)). The positive charge on the graphene layer now screens the negative gate bias as shown in panel V of Figure 1(g). Like the positive bias condition, this screening leads to the flatband condition at an effective negative bias when we start the forward run resulting in the anti-hysteretic transfer characteristics. The sweep-rate independence (Supplementary Figure S4) and range-tunability of the anti-hysteresis (Figure 1(d) and (e)) suggests (nearly) relaxation-free charge transfer between the channel and the FG which is facilitated by crystallinity of the hBN layer and atomically pristine van der Waals interfaces.

The plasticity of vertical charge transfer in the MoS2 floating gate device allows non-volatile conductance change under pulsed gate operation. This behaviour is analogous to biological synapses where the application of an excitatory or inhibitory pre-synaptic pulse has the effect of increasing or reducing the conductance of the synapse respectively. In this case, the gate acts as the pre-synaptic terminal and controls the conductance of the MoS2 channel/synapse using a sequence of pulses. The increase and decrease in conductance are known as potentiation and depression of the synapse respectively. This is performed by applying short time period (0.1 s) voltage pulses at the gate terminal while simultaneously tracking the change in drain current. The channel conductance continuously increases for every excitatory pulse ($-4$ V pulse in top panel of Figure 2(a)) following an approximately linear pattern and decreases on application of an inhibitory pulse ($+3$ V pulse in the third panel from top of Figure 2(a)). Figure 2(b) and (c) compares the nature of synaptic response in devices with and without an extension of the FG respectively. Starting from the rest condition a set of twelve excitatory pulses ($-4$ V pulse height and 0.1 s pulse width) followed by twelve inhibitory ones ($+3$ V pulse height and 0.1 s pulse width) were applied at the gate terminal twice and the change in drain current was recorded after each pulse. The device with an extended FG (D4) shows a considerable change ($\lesssim$ 80$\%$) in channel conductance (Figure 2(b)), while a negligible change is observed ($\lesssim$ 2$\%$) in the device without an extended FG (D9) (Figure 2(c)). The current values plotted in Figure 2(b) and (c) shows the average current over a period of one second after the pre-synaptic pulse has been removed and the channel conductance has settled down to its final value (see Supplementary Section IX). The long term plasticity is robust and persists even after a large number of potentiation and depression cycles which was limited to 20 in the current experiment (Figure 2(d)). We observe potentiation and depression curves similar to previously reported synaptic devices 15; 16; 17; 18; 19; 20; 22 although the shape of the excitatory post-synaptic current ($I_{sd}$ vs time plots in Figure 2(a)) in our case is different from that observed in previous reports  15; 16; 17; 20; 21; 22. As a result of the unique transport mechanism of these devices, we observe low conductance values during the time period of an excitatory (potentiation) pulse while higher values of conductance are seen during an inhibitory (depression) pulse (Figure 2(a)). Additionally, the inhibitory nature of positive gate voltage pulses leads to negative values for the short term plasticity based paired-pulse facilitation (PPF) index (see Supplementary Section X for details). We find that pulses of similar time period but larger magnitude produce a larger change in conductance. This is illustrated in Figure 2(e) for multiple potentiation cycles. A similar effect is observable on increasing the time period of the pulse while keeping the magnitude same (Figure 2(f)).

For a quantitative analysis of the change in $I_{sd}$ during both potentiation and depression pulses, we consider the bi-directional tunneling of charge across the hBN layer. As discussed in Figure 1(g), the channel conductance varies due to the tunneling of charges in or out of the channel through a hBN tunnel barrier. In Figure 3(a), we plot the absolute value of charge transferred per excitatory ($-4$ V) or inhibitory ($+3$ V) pulse for the device D4. This is computed by finding the effective gate bias necessary to induce the change in drain current ($\Delta I_{sd}$) observed for a single potentiation/depression of the channel. The magnitude of charge exchanged during a potentiation or depression event can be estimated from $\Delta Q=\Delta V_{g}\times C_{self}$ where $\Delta V_{g}=\Delta I_{sd}/g_{m}$ with $g_{m}$ the transconductance and $\Delta V_{g}$ the effective change in gate voltage for a single pre-synaptic pulse. Here, $C_{self}$ ($\approx$ 8$\epsilon_{0}\sqrt{A_{FG}}$), $\epsilon_{0}$ and $A_{FG}$ are the self-capacitance of the FG, permittivity of free space and area ($\approx$ 45000 $\mu$m2) of the FG, respectively. The computed values of $\Delta Q$ for the potentiation and depression cycles depicted in Figure 2(b) ($V_{sd}$ = 0.01 V) are shown in Figure 3(a). We find $\Delta Q$ to be reasonably constant, being $\approx$ 2$\times$10*-16* coulomb per pulse. To estimate the tunneling current ($I_{tunnel}$), we assume Fowler Nordheim type electric field dependent tunneling in our devices as reported previously 60 for hBN tunnel barriers. The tunneling current is given by

[TABLE]

where $A_{ch}$ is the channel area and $\phi_{b}$ the barrier height for tunneling. The effective electron mass for hBN, $m^{*}=$ 0.26$\times m$, where $m$ is the free electron mass. Here, $h$ and $q$ represent the Plank’s constant and electron charge, respectively, while $d\approx$ 5.8 nm is the thickness of the hBN layer (see Supplementary Figure S2). The barrier height ($\phi_{b}$) is computed from the device band structure using known values for the work function of graphene and MoS2 along with the electron affinity and band gap of hBN as shown in Figure 3(b) 31. We find a barrier height of 3.1 eV for potentiation which involves transfer of holes from MoS2 to FG and 2.6 eV for depression which involves transfer of electrons (Figure 3(b)). In Figure 3(c) we have plotted the tunneling charge ($I_{tunnel}\times$ pulse width), calculated from Eq. 1 for both potentiation and depression as a function of the tunneling bias ($V_{tunnel}$). $V_{tunnel}$ for the current devices are obtained by graphically solving Eq. 1 for known values of the tunneling charge from Figure 3(a), which yields the potential across the hBN layer to be 3.36 V and 2.61 V for potentiation and depression events respectively (Figure 3(c)). To verify this, we measure the effective bias across the hBN tunnel barrier (denoted by the difference in Fermi level between the graphene and MoS2 layers in panel V (potentiation) II (depression) in Figure 1(g)) from the device transfer characteristics (Figure 3(d)). The tunneling voltage for potentiation (depression) is given by the difference between the threshold voltage for forward (reverse) sweep and the excitatory (inhibitory) pulse height. This method yields $V_{tunnel}$ values of 3.52 V for potentiation and 2.5 V for depression (Figure 3(d)), which are similar to those obtained from Fowler Nordheim modelling (Figure 3(c)), confirming the charge tunneling mediated synaptic behaviour in our devices. Since the synaptic activity originates from the tunneling of charges between the channel and the FG, we also observe synaptic plasticity in a two terminal geometry. However, the device operates at large current levels ($\approx$ few $\mu$A) making it energetically unfavorable for neuromorphic applications (see Supplementary Section VIII for details).

Apart from the systematic modification of channel conductance in response to pre-synaptic pulsing, synaptic memories are also meant to follow specific learning mechanisms which guide their response to a train of applied pulses. Here, we demonstrate a very common learning process of the human brain known as spike time dependent plasticity (STDP) using the current device 61; 62; 63. In this case, the conductivity of the synapse is a function of the time difference between the pre and post synaptic pulses. This is performed using a mapping function which converts the time difference between the pulses to the magnitude of pre-synaptic pulse applied. The experimental procedure followed is demonstrated in Figure 4(a) and is similar to the process detailed in Ref. [16] (see Supplementary material section V & VI for more details). Depending on the mapping function used (details provided in Supplementary section VI), we obtain synaptic responses which are symmetric (symmetric STDP) (Figure 4(c)) or asymmetric (asymmetric STDP) (Figure 4(b)) with respect to the time difference between the pre and post synaptic pulses. To demonstrate the effect, we have plotted the percentage change in channel conductance $\Delta G\%$ with the time difference $\Delta t$. $\Delta G\%$ is given by

[TABLE]

where $G_{intial}$ and $G_{final}$ are the channel conductance before and after the application of the synaptic pulse respectively. We observe large changes in the synaptic weight for small time differences between the pre and post synaptic pulse in both types of synaptic learning (Figure 4(b) and (c)). For the asymmetric case (Figure 4(b)), we see a sharp decrease in channel conductance for a non causal event, $i.e.$ $\Delta t\less 0$, while there is a sharp increase in conductivity for a causal event, $i.e.$ $\Delta t\geq 0$. To obtain a time constant for the potentiation and depression pulses we fit an exponential to the STDP data in Figure 4(b) (black solid lines) as follows 62

[TABLE]

$\tau_{+}$ and $\tau_{-}$ denote the characteristic scale of time difference between the pre and post synaptic pulses for which there is a considerable change in the synaptic weight. For the current device we find these values to be 0.34 s and 0.6 s for potentiation and depression pulses respectively. These values can be tuned by changing the mapping function (Supplementary section VI). For the symmetric STDP case (Figure 4(c)) we find that the channel conductivity depends only on the absolute time difference between the synaptic inputs $\mid\Delta t\mid$. The change in channel conductivity is $\approx$ 100$\%$ leading to a very robust demonstration of spike time dependent learning which is independent of the applied bias (Figure 4(b) and (c)).

To evaluate the energy efficiency of the our synaptic transistor, note that the energy dissipated for a single pulse is given by

[TABLE]

where $I_{sd}$ is the average current during the pulse, $t_{pulse}$ is the time period of the pulse and $V_{sd}$ the drain bias. Figure 5(a) plots the energy dissipation as a function of pulse width for both potentiation ($-4$ V pulse height) and depression ($+3$ V pulse height) pulses at a drain bias ($V_{sd}$) of 0.01 V for the synaptic device D4. Since the channel conductance is lower during a potentiation pulse and higher during a depression pulse, we observe a higher energy loss during depression (Figure 5(a)). The observed energy dissipation $\approx$ 20 pJ per pulse for depression is similar to synaptic devices previously reported 23; 24; 25; 26; 27; 28; 29; 30; 17; 20; 15 (Figure 5(b)). Notably, this is about five decades lower than similar devices operated in two terminal geometry ($\approx$ 1 $\mu$J per pulse for same pulse duration) 46 and $\sim 1-2$ decades lower than complementary MOS devices 64; 20. We also note that the energy dissipation in our devices scale linearly with pulse width (Figure 5(a)) leading to a decrease in energy consumption for lower values of $t_{pulse}$ (Eq. 4). For our MoS2 based synaptic transistor, we find that the extrapolated energy dissipation for a pulse width of $\approx$ 100 $\mu$s is $\approx$ 20 fJ (indicated in Figure 5(a)), which is comparable to that in Ref. [15], reiterating the benefits of using TMDC based synaptic transistors for enhanced power efficiency. Additionally, we now know that both in-plane and cross-plane charge and heat transport in van der Waals heterostructures are strongly temperature dependent and can be tuned accurately with external electric fields. 65; 37 This allows a holistic integration of transport layer, heating layer and floating gate in a bottom up fashion, 66 opening up a wide range of possibilities including the implementation of biorealistic neuromorphic realizations for example, by electro-thermal pulsing in a second order memristor. 67

In conclusion, we have successfully fabricated a charge-tunneling based synaptic transistor using ultrathin molybdenum disulphide channels. Repeated potentiation and depression of the channel conductance is demonstrated along with spike timing dependent synaptic plasticity while maintaining a desirable energy efficiency. We provide a new framework for solid state synaptic devices free of electrochemical reactions which may be utilised in future neuromorphic applications.

Acknowledgement

We acknowledge the Department of Science and Technology (DST) for a funded project. The authors would also like to thank National Nanofabrication Facility (NNFC), CENSE, IISC and Micro and Nano Characterization Facility (MNCF), CENSE, IISC for fabrication and characterization facilities provided.