Low temperature (< 200{\deg}C) solution processed tunable flash memory device without tunneling and blocking layer

TL;DR

This paper presents a low-temperature solution-processed flash memory device that eliminates the need for tunneling and blocking layers by leveraging high intrinsic charge traps and low leakage current in inorganic dielectric films heated at 200°C or below.

Contribution

It introduces a novel tunable flash memory device fabricated at low temperatures without tunneling and blocking layers, utilizing high trap density and low leakage in inorganic dielectric films.

Findings

Achieved high intrinsic charge trap density (>10^12 cm^-2)

Demonstrated low leakage current (<10^-7 A.cm^-2)

Memory storage tunable up to 96% with heating temperature

Abstract

Intrinsic charge trap capacitive non-volatile flash memories take a significant share of the semiconductor electronics market today. It is a challenge to create intrinsic traps in the dielectric layer without high temperature processing steps. While low temperature processed memory devices fabricated from polymers have been demonstrated as an alternative, their performance degrade rapidly after a few cycles of operation. Moreover conventional memory devices need the support of tunneling and blocking layers since the memory dielectric or polymer is incapable of preventing memory leakage. The main issue in designing a memory device is to optimize the leakage current and intrinsic trap density simultaneously. Here we report a tunable flash memory device without tunneling and blocking layer by combining the discovery of high intrinsic charge traps ($>$10$^{12}$ cm$^{-2}$) together with low leakage current($<$10$^{-7}$ A.cm$^{-2}$) in solution derived, inorganic, spin$-$coated dielectric films which were heated at 200$^\circ$C or below. In addition, the memory storage is tuned systematically upto 96% by controlling the trap density with increasing heating temperature.

Full text

Low temperature ($<$ 200∘C) solution processed tunable flash memory device without tunneling and blocking layer

Sandip Mondal1,2, V Venkataraman2

1SanDisk India Device Design Center, Bangalore 560103, India

2Department of Physics, Indian Institute of Science, Bangalore 560012, India

Intrinsic charge trap capacitive non-volatile flash memories take a significant share of the semiconductor electronics market today. It is a challenge to create intrinsic traps in the dielectric layer without high temperature processing stepsHsinChiangYou2006 . While low temperature processed memory devices fabricated from polymers have been demonstrated as an alternativeLee2007 ; Kapetanakis2008 ; Tsai2013 ; Chiu2014a ; Chiu2015 ; Wei2012 , their performance degrade rapidly after a few cycles of operationBaeg2014 ; Park2015a ; Kim2010a ; Faber2009 ; Park2010c ; Han2011a ; Wang2010 . Moreover conventional memory devices need the support of tunneling and blocking layers since the memory dielectric or polymer is incapable of preventing memory leakageKim2010b ; Yi2016a ; Lee2009 . The main issue in designing a memory device is to optimize the leakage current and intrinsic trap density simultaneouslyLee2011b . Here we report a tunable flash memory device without tunneling and blocking layer by combining the discovery of high intrinsic charge traps ($>$1012 cm-2) together with low leakage current($<$10*-7* A.cm*-2*) in solution derived, inorganic, spin$-$coated dielectric films which were heated at 200∘C or below. In addition, the memory storage is tuned systematically upto 96% by controlling the trap density with increasing heating temperature.**

Today’s semiconductor memory technology is dominated by silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile flash memory which is based on intrinsic charge traps in silicon-rich silicon nitride films deposited by high temperature ($\sim$ 780oC) compatible chemical vapor depositionXue2012 ; Liu2012 . The intrinsic charge traps in silicon-rich silicon nitride films were first reported in 1967 Hu1967 and the first flash memory device incorporating silicon nitride charge storage was demonstrated in 1980’s Junction1989 . However the trap density and distribution are difficult to control in such materialPark2006 . Traps can be increased by ion bombardment and plasma-passivationLiu2012 , but the leakage current increases. Alternate high-k dielectrics such as TiO2, HfO2, ZrO2, etc. are excellent insulators for transistor applications Avis2011 ; Suzuki2009b ; Dutta2013a ; Kumar2015a , but do not have the intrinsic charge trapping properties as silicon nitride. Although solution processed HfO2 has been used to fabricate SONOS type flash memoryHsinChiangYou2006 , the devices required the support of additional dielectric layers which were deposited by sophisticated ultrahigh vacuum techniques with high temperature processing steps to improve the memory leakage. For most dielectrics, precursor solutions with organic solvents result in poor leakage current which can be improved to some extent by high heating temperatureMondal2017 . However the high temperature heating process lowers leakage current but reduces trap density. Hence, the main challenge is to simultaneously achieve deep intrinsic charge traps together with very low leakage current at low processing temperatures. There are a few reports on solution processed flash memory by using polymer materialsChang2013 ; Shih2015 , but these devices degrade after only few cycles of operation in normal environmental conditions and they are not capable of working at higher temperatures.

In the last few years, a novel inorganic, completely carbon free, water soluble dielectric Aluminium Oxide Phosphate (ALPO), has been successfully employed as gate dielectric in high performance TFTs that are competitive with a-Si TFTsKim2011 . Due to its very low leakage current density, it was used recently as tunneling and blocking layer to fabricate fully solution processed two terminal capacitive flash memory devicesMondal2016 with CdTe-NP as the charge storage center. Nevertheless a fully spin$-$coated low temperature processed (below 200∘C) high$-$performance flash memory device without tunneling and blocking layers has not been reported so far.

Here we report the discovery of ultra-high number of intrinsic charge traps ($>$1012cm*-2*) in low temperature solution processed inorganic ALPO dielectric. At the same time, the leakage current is sufficiently low ($<$ 10*-7* A.cm*-2*) for flash memory operation without incorporating tunneling or blocking layers. In addition, the number of traps can be varied with heating temperature, which is strongly correlated with the oxygen vacancy concentration in the film. Furthermore, we demonstrate optimized robust high performance fully solution processed inorganic oxide precursor based flash memory devices without tunneling and blocking layer, where the processing temperature does not exceed 200∘C. Our devices outperform other similar memory devices reported earlierLee2007 ; Kapetanakis2008 ; Tsai2013 ; Chiu2014a ; Chiu2015 ; Wei2012 .

A schematic of typical device architecture is depicted in Fig. 1a. ALPO is deposited by spin-coating a completely inorganic, carbon free and aqueous precursor solution on low-doped $p$-silicon substrate ($p\sim$4$\times$1015 cm*-3*). After deposition various substrates are heated at different temperatures including at low temperature such as 200∘C. The inset of Fig. 1a shows a schematic of molecular structure of the low temperature (200∘C) processed ALPO. The thickness of the deposited film is measured by ellipsometry (see Section I, Supporting Information) and verified by cross-sectional scanning electron microscope (SEM) image (Fig. 1b). Such prepared films are found to be atomically smooth showing surface roughness to be $\sim$0.08 nmMeyers2007a ; Mondal2017 which is determined by the atomic force microscopy (AFM) with an areal scan over 50$\mu$m$\times$50$\mu$m (top-panel,Fig. 1c). An aluminum contact is deposited thereafter by thermal evaporation for the purpose of electrical measurement. The deep level charge storage in the deposited ALPO is characterized via capacitance-voltage (CV) measurement. An optical image of device on chip has been shown in the bottom-panel of Fig. 1c.

Intrinsic trap levels in ALPO cause a hysteretic output of the CV traces highlighting the memory-like behavior of the devices (Fig. 1d). Further, the trap density can be varied by heating the samples at different temperatures which alters the hysteresis-window. For example, an as-prepared sample shows a memory window of $\sim$12.9 V (left-panel) which corresponds to a trap density of n $\sim$5.65$\times$1012 cm*-2*, where as, an ALPO-film heated at 200∘C for one hour shows a hysteresis window of $\sim$17.5 V which corresponds to the trap density of n $\sim$ 6.37$\times$1012 cm*-2*. When the film is heate at 600∘C, the trap density drastically reduces (n $\sim 10^{11}$ cm*-2*) causing a significantly low hysteresis window ($\sim 2.2$ V, right-panel). A similar variation of electronic traps with heating temperature is also observed from the devices which are made with lower thickness ALPO film, however, there is no affect due to change in device dimension (see Section III, Supporting Information). From the sweep direction of the CV curve it is inferred that gate injection of carriers controls the memory operation. Although conventional flash memory architecture follows channel injection of carriersLiu2012 , the interface degrades fast in such devicesWu2008 . Thus, compared to channel injected devices, gate-injected devices show higher endurance which is one of the key requirements of memory operationLue2007 . Because of such advantages, the quest for efficient gate-injected flash memory devices is ongoingWu2008 ; Lue2007 ; Lue2008 ; YeolYun2014 . A systematic change in the hysteresis window as a function of heating temperature is presented in Fig. 1e, where, solid squares are the experimental data, shaded region is guide to the eye and the width of the shaded region indicate the standard deviation around their mean vertical position estimated from similar results. Use of higher heating temperature ($>600^{\circ}$C) causes a dramatic reduction in trap density, thus reducing the hysteresis window. A 96% reduction in trap density ($n\sim 2.19\times$1011 cm*-2*) is observed at an heating temperature of $\sim$800∘C resulting a memory window of 0.7 V only. In addition, a negligible degradation in CV hysteresis is obtained from as prepared devices even after 5 years of storage in ambient conditions (see Section IV, Supporting Information). This demonstrates that the devices are very stable for long term application, in spite of the water absorbing property of ALPOPerkins2016 ; Anderson2015 .

In order to investigate the robustness of intrinsic charge storage property of ALPO, we demonstrate a series of memory operations on the metal-insulator-semiconductor structured (MIS) two terminal capacitive devices which were heated at 200∘C. The memory characterization focuses upon the flat band voltage shift ($\Delta$VFB) due to the voltage sweep operation (i.e. erasing($E$) or programming($P$) operation) on the gate terminal of the devices. A device is programmed ($P$) or erased ($E$) by sweeping the gate voltage at a slow rate Mondal2016 . Sequential $P$ and $E$ cycles set and reset the flat band voltage reversibly and is confirmed from the nearly constant $V_{FB}$ values obtained from multiple $E$-$P$ cycles (Fig. 2a). Two of the $C$-$V$ traces corresponding to the 1st and 20th $E$-$P$ traces are shown in the inset of Fig. 2a. Nearly constant values of $V_{FB}$ in $E$ and $P$ states indicate that $E$-$P$ cycles have negligible effect on the memory state thus indicating high reliability of the devices.

Frequency and gate bias dependent $\Delta~{}V_{FB}$ changes are shown in Fig. 2b. Flatband voltage window shows insignificant change within the range of 10-1000 kHz frequency of excitation voltage. Such behavior is attributed to the slow trapping de-trapping phenomena which thus indicates that the states can be probed by deploying high speed CV measurement. With different gate bias voltages $\Delta~{}V_{FB}$ increases first and then shows a decrease. Such behavior appears because of the competition between the trap filling and charge losses. Initially ($\sim$5-20 V) as the sweep voltage is increased, larger electric field causes more charge injection into the traps, hence, the hysteresis width increases. Beyond 20 V, which corresponds to an electric field of $\sim$1.2 MV.cm*-1*), the high leakage current (see Section V, Supporting Information) leads to increased charge loss, thus a reduction in hysteresis window is observed (Fig. 2b). A hysteresis window of 15 V is obtained for a sweep voltage range of $\pm$ 15 V which corresponds to an optimum memory window of 50% of the total sweep-range. The result of 50% window for intrinsic traps in ALPO exceeds previously reported valuesLehninger2015c for other dielectrics. It is known from literature that the high performance operation of flash memory stack should not have leakage current density more than 10*-6* A.cm*-2* when operated with an electric field of 1 MV.cm*-1* ChiChangWu2010 . The ALPO devices show a leakage current density of $\sim$4.5$\times$10*-8* A.cm*-2* only at -1 MV.cm*-1* electric field. Such low leakage current not only meets the criteria for the application of high-performance flash memory devices, but also outperforms other solution processed inorganic dielectrics namely Al2O3Avis2011 , HfO2Suzuki2009b , ZrO2Dutta2013a , and TiO2Kumar2015a , which show typical leakage currents $\sim$10*-5* A.cm*-2*, $\sim$10*-7* A.cm*-2*, $\sim$10*-2* A.cm*-2* and $\sim$10*-5* A.cm*-2* respectively at 1 MV cm*-1*. This observation for ALPO also ensures that high quality flash memory devices can be fabricated without the need of blocking or tunneling layers.

True program ($P$) and erase ($E$) operations are realized by application of positive and negative square pulses respectively, Whereas the read operation is performed by using triangular pulses having shorter time periods (T $\sim$4 $\mu$s). Since high speed voltage sweep does not alter the memory state (Fig. 2b), shorter triangular pulses are expected to probe the $E$ and $P$ states without disturbing them. By varying the width of the square-pulses, various memory-windows ($V_{FB}|_{P}-V_{FB}|_{E}$) are obtained and shown in Fig. 2c. While using a single pulse to program or erase, a pulse width of 500 ms can set the memory window to be as large as $\sim$9 V. The program/erase speed of these devices is found to be $\sim$200 ms which is significantly faster compared to other solution processed flash memory devicesLehninger2015c ; Park2014 ; Yun2009 ; Bar2015c ; Chen2011 . During programming and erasing, a maximum charge capturing efficiency of 7.46 % is estimated while operating with a gate electric field of 2.37 MV/cm (see Section VI, Supporting Information). This capturing efficiency is higher than the reported values obtained from other dielectricsZhang2007 .

To check for any disturbance of the program/erase state during the read operation, the device is set to $E$ or $P$ states first with a single long square pulse ($T\sim 0.5~{}$s, see Fig. 2c) and then multiple high-frequency triangular ($T\sim 4~{}\mu$s) pulses were applied representing multiple read operations. Figure 3a shows the statistical distribution of $V_{FB}$ values obtained from such multiple read operations for both the $E$ and $P$ states. Narrow distributions of $V_{FB}$ indicate low read-disturb for both the states. Inset of Fig. 3a shows typical $C$-$V$ traces for $E$, $P$ and read operations. Here two red and two green lines indicate back-and-forth sweep of the voltage ($V_{G}$) using the high speed triangular read pulse probing the $P$ and $E$ states respectively.

Erase-program operation over 10 k cycles shows no degradation in memory window thus demonstrates high endurance (Fig. 3b). In fact, with the increasing operation cycle memory window increases which may be attributed to the generation of additional trap states because of electrical stress. Data retention was tested by programming a fresh device at room temperature with pulses of amplitude 33 V and duration 500 ms. The device shows almost no change in memory window within $\sim$104s which was the limit of experimental time scale. This is the highest reported retention time for any memory device without additional tunneling and blocking layers. Even after 10 k $P$/$E$ cycles devices show a degradation of only 9% memory window after $\sim 10^{4}$s (Fig. 3d). Temperature dependent data retention was also tested and presented in Fig. 2e. After 104s of operation a memory window loss of 25% and 50% are observed at 60∘C and 80∘C respectively. The reliability is also tested on the device made with lower thickness of ALPO film (91 nm) which shows equivalent performance as obtained from the other devices(see Section VII, Supporting Information)

To examine the scalability of these low temperatures processed memory devices, we prepared and characterized more than 40 devices. Statistical distribution of memory window for all these devices are shown in Fig. 3f. 80% of devices lie within the expected memory window (3-4V) when programmed with $\pm$33 V pulse height and 300 ms duration. The remaining 20% devices show a memory window of less than 3V. These preliminary results show sufficiently high yield for large scale production needed for practical applications.

Microscopic origin of memory operation is understood from the temperature controlled trap density variation which is confirmed from photo-emission spectroscopy (XPS). Multiple samples were prepared at different heating temperatures and studied with XPS. The shape of the oxygen peak changes systematically with respect to heating temperature (Fig. 4a). De-convolution of XPS signal into respective peaks of oxygen vacancies(M-Ovac), metal hydroxide(M-OH) and lattice oxygen(M-O) helps understanding the contributions of respective states (Fig. 4b-d). The ALPO film which was heated at 200∘C has similar ratio (atomic %) of aluminum (Al), oxygen (O) and phosphorous (P) as that of the mother solution (see Section VIII, Supporting Information). Due to addition of HCl in the ALPO precursor, a small percentage of chlorine is observed (see Section IX, Supporting Information) in low temperature processed ALPO film. It is observed that M-Ovac intensity sharply decreases with increase in heating where temperature reaches above 200∘C (Fig. 4b-d and Section X of Supporting Information). As the heating temperature increases, hydrogen is lost as water vapor and the film becomes denser. The M-O peaks increase with higher heating temperature (Fig. 4e-f ). This is consistent with the reduction in the number of oxygen vacancies and consequently lower trap density in samples heated at higher temperature. A quantitative comparison between the peak intensity and the trap density of the heated film reveals a strong correlation between the oxygen vacancies and trap densities (see Section X, Supporting Information), thus indicating that the oxygen vacancies are the responsible entities for memory states.

In conclusion we have shown fabrication and high quality performance of low temperature processed ($\lesssim$200 ∘C) inorganic flash memory devices which do not require tunneling or blocking layers. Simple sample fabrication technique involving spin-coating of solution is another advantage. Narrow distribution of memory window obtained from more than 40 samples indicates the scalability of the fabrication method. In spite of having no tunneling and blocking layers, these devices show extremely low leakage current which is one of the key features of memory operation, and demonstrate high endurance, high retention, thus, outperforming other solution processed memory devices reported so far. Temperature dependent control on trap density also helps optimizing the memory window. ALPO based devices paves the way for designing a new class of scalable two terminal flash memory devices for practical applications.

Methods

**Material growth: ** Precursor solution of Aluminium Oxide Phosphate, ALPO [Al2O3-3X (PO4)2X] in water (18 M$\Omega$ cm) was prepared with Al(OH)3 (99%, Alfa Aesar, USA) in 2 mole equivalents of HCl (AR Grade, Thermo Fisher Scientific, USA) and an appropriate amount of H3PO4 (ExcelaR Grade, Thermo Fisher Scientific, USA) was added to obtain P/Al = 0.5 with concentration of 0.5 M . The solution was stirred under heat of 90∘C in a water bath for 24 hours.

Device fabrication: ** Two terminal MIS structures were fabricated on piranha cleaned [H2SO4:H2O2 = 3:1] lightly doped silicon substrate (p$-$Si). The ALPO solution was spin-coated at 3000 rpm for 30s to form the gate dielectric. The films were then heated at 150oC for 1 min. This process was repeated for 2-3 times to achieve the desired thickness. The sample was exposed to oxygen plasma for 5 to 10 mins at 0.5 mbar pressure before deposition of each layer. Such fabrication process may help generation of stable traps in ALPO below 200∘C. Typically, ALPO based devices are treated at high temperature ($>$350∘C) to achieve better dielectric performance, thus, most of the reported devices do not show any memory effectKim2011 . For control devices the film was further heated at 800oC for one hour in ambient to achieve the trap free oxide. A 200 nm aluminium gate was deposited by thermal evaporation at $\sim$ 10-6 mbar pressure. Before deposition of the top aluminium gate, the ALPO films were heated at different temperature in a preheated furnace for one hour. All devices were stored under ambient conditions and no degradation of CV curves was found even after three years.

**Characterization: ** ALPO precursor solutions prepared with different concentrations and P/Al ratios were optically characterized using a UV-Visible spectrophotometer. They are all transparent in visible wavelength range with the main absorption peak in the ultra-violet range at 235 nm. After spin coating and heating, the film shows a refractive index 1.5 (see Section I, Supporting Information) with negligible absorption at 550 nm as measured by ellipsometry (M-2000, J.A. Woollam Co. Inc., USA). The thickness of ALPO film on silicon substrate extracted from ellipsometry is 139 nm and verified with cross-sectional SEM (Ultra 55, Carl Zeiss). The surface of the ALPO film is atomically smooth with a roughness of 0.08 nm as measured by AFM (ND$-$MDT, Russia). The CV curve was measured with HIOKI 3532 LCR meter and Keithley 2400 source meter. Agilent Device Analyzer B1500A was used to measure the IV characteristics in ambient environment. The leakage current and CV measurements were performed on more than 50 devices. The entire measurement was done in continuous mode of the instrument. The high speed CV measurement was performed with home made CV measurement systemMondal2016 . The XPS measurements were carried out by AXIS 165 with Al K$\alpha$ radiation (9mA, 13keV, 1486.6 eV) in ultra$-$high vacuum. The XPS spectra were calibrated with C 1s peak (284.6 eV).

Acknowledgment

This work was supported by the grant (MITO$-$084) of Center for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bengaluru, India. S.M. would like to thank Dr. Kallol Roy for useful discussions during manuscript preparation. S.M. also thanks Chandan and Arvind Kumar for help to analyze the data. S.M. also thanks the Rajiv Gandhi National Fellowship of the University Grants Commission (UGC) for fellowship support.

Author contributions

S.M., V.V. conceived the project. S.M. designed and performed the experiments, completed characterization of the fully solution processed flash memory device. S.M. analyzed results and wrote the paper.

Additional information

Supplementary information is available in the online version of the paper. Correspondence and requests for materials should be addressed to S.M.