Architecture of a Quantum Multicomputer Optimized for Shor's Factoring Algorithm
Rodney Doyle Van Meter III

TL;DR
This paper presents optimized algorithms for quantum modular exponentiation that significantly accelerate Shor's factoring algorithm, and analyzes multicomputer architectures with different interconnect topologies and error correction schemes for large-scale quantum factoring.
Contribution
It introduces new quantum algorithms reducing modular exponentiation complexity and evaluates multicomputer architectures with specific interconnects and error correction for large number factoring.
Findings
Algorithms reduce modular exponentiation latency from O(n^3) to as low as O(n^2 log n)
Quantum multicomputer with serial links can effectively factor 1024-bit numbers
Error correction with Steane code protects data even with 1% teleportation failure rate
Abstract
The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor's algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation. My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n^3) to O(n log^2 n) or O(n^2 log n), depending on architecture. Calculations show that these algorithms are one million times and thirteen thousand times faster, when factoring a 6,000-bit number, depending on architecture. Extending to the quantum multicomputer, five different qubus interconnect topologies are considered, and two forms of…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography
