Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

TL;DR

This paper introduces a hierarchical statistical model for fault distributions in IC manufacturing, capturing variations across regions and wafers, and integrates Bayesian methods for yield analysis.

Contribution

It develops a hierarchical framework for modeling process-induced faults using compound distributions, unifying fault density analysis across different levels and incorporating Bayesian approaches.

Findings

Hierarchical fault distribution models effectively describe fault variability.

The approach provides in-process yield loss measures.

Bayesian methods are naturally integrated into the hierarchical framework.

Abstract

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution and the compound binomial distribution are treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. With respect to applications, hierarchies of yield means and yield probability-density functions are considered and an in-process measure of yield loss is introduced. It is shown that the hierarchical approach naturally embraces the Bayesian approach.