The BlueGene/L Supercomputer
Gyan Bhanot, Dong Chen, Alan Gara, Pavlos Vranas
TL;DR
The paper describes the architecture and design of the BlueGene/L supercomputer, highlighting its massively parallel structure, node components, network connections, and overall performance capabilities.
Contribution
It provides a detailed technical overview of the BlueGene/L supercomputer's architecture, including node design, network topology, and performance specifications.
Findings
Total peak performance of 360 Teraflops
Connected 65,536 nodes in a 3D torus topology
Total memory capacity of 16 TeraBytes
Abstract
The architecture of the BlueGene/L massively parallel supercomputer is described. Each computing node consists of a single compute ASIC plus 256 MB of external memory. The compute ASIC integrates two 700 MHz PowerPC 440 integer CPU cores, two 2.8 Gflops floating point units, 4 MB of embedded DRAM as cache, a memory controller for external memory, six 1.4 Gbit/s bi-directional ports for a 3-dimensional torus network connection, three 2.8 Gbit/s bi-directional ports for connecting to a global tree network and a Gigabit Ethernet for I/O. 65,536 of such nodes are connected into a 3-d torus with a geometry of 32x32x64. The total peak performance of the system is 360 Teraflops and the total amount of memory is 16 TeraBytes.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsInterconnection Networks and Systems · Parallel Computing and Optimization Techniques · Embedded Systems Design Techniques