QCDOC: A 10-teraflops scale computer for lattice QCD
D. Chen, N. H. Christ, C. Cristian, Z. Dong, A. Gara, K. Garg, B. Joo,, C. Kim, L. Levkova, X. Liao, R. D. Mawhinney, S. Ohta, T. Wettig
TL;DR
The paper introduces QCDOC, a specialized supercomputer architecture designed specifically for lattice QCD calculations, featuring high-performance nodes with integrated processors and fast communication links.
Contribution
It presents a novel architecture for a supercomputer optimized for lattice QCD, integrating processing and communication on a single chip for enhanced performance.
Findings
Designed a node with a PowerPC processor and high-speed memory
Achieved 1 Gflops performance per node
Enabled scalable, high-speed communication between nodes
Abstract
The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from ``QCD On a Chip''.
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