A 16-channel Digital TDC Chip with internal buffering and selective readout for the DIRC Cherenkov counter of the BABAR experiment

TL;DR

This paper presents a 16-channel digital TDC chip designed for the DIRC Cherenkov counter in the BaBar experiment, featuring internal buffering, selective readout, high linearity, low dead time, and low power consumption.

Contribution

The paper introduces a novel 16-channel digital TDC chip with integrated buffering and programmable readout tailored for high-energy physics experiments.

Findings

Linearity better than 80 ps rms

Dead time loss less than 0.1% at 100 kHz per channel

Power dissipation under 100 mW

Abstract

A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns, the conversion time 32 ns and the full-scale 32 mus. The data driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The time measuring scale is constantly locked to the phase of the (external) clock. The linearity is better than 80 ps rms. The dead time loss is less than 0.1% for incoherent random input at a rate of 100 khz on each channel. At such a rate the power dissipation is less than 100 mw. The die size is 36 mm2.