Present Status of VEPP-5 Control System

TL;DR

This paper describes the current hardware and software architecture of the VEPP-5 control system, highlighting its components, networking, and control strategies for accelerator equipment.

Contribution

It provides a comprehensive overview of VEPP-5 control system hardware and software, detailing integration of various controllers and network protocols.

Findings

Use of CAMAC blocks and crate controllers for hardware control

Implementation of TCP/IP networking for workstations

Adoption of a three-level software model

Abstract

This report concerns the present status of VEPP-5 control system. The control system hardware consists of CAMAC blocks, a set of crate controllers based on INMOS transputers and ICL-1900 architecture processor Odrenok, and Pentium-based workstations. For small tasks simple serial CAMAC controllers are used. For slow controls of power supplies the CANBUS is begun being used. The workstations are running Linux and are connected via local net using TCP/IP. Odrenok crate controllers are joined into other local net and are used for control of equipment in high voltage pulse condition (klystron gallery). Transputer crate controllers are linked directly to the server computer and are used for high performance diagnostics (BPM). The three-level software complies the so-called ``standard model''.