Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs

TL;DR

This paper presents an automated hardware synthesis approach for a hybrid reconfigurable CPU that integrates Philips CPLDs, enabling transparent hardware implementation of time-critical code segments for improved performance.

Contribution

It introduces a high-level architecture and a compilation chain that automatically translates assembly code segments into hardware netlists for a hybrid CPU with Philips CPLDs.

Findings

Successful hardware implementation of time-critical segments

Transparent integration from programmer perspective

Application examples demonstrating effectiveness

Abstract

A high-level architecture of a Hybrid Reconfigurable CPU, based on a Philips-supported core processor, is introduced. It features the Philips XPLA2 CPLD as a reconfigurable functional unit. A compilation chain is presented, in which automatic implementation of time-critical program segments in custom hardware is performed. The entire process is transparent from the programmer's point of view. The hardware synthesis module of the chain, which translates segments of assembly code into a hardware netlist, is discussed in details. Application examples are also presented.