Noise Limited Computational Speed

TL;DR

This paper investigates how noise fundamentally limits the speed of computation in transistor logic gates, deriving an optimal idle time to minimize errors caused by noise.

Contribution

It introduces a two-state model to analyze noise effects on logic gates and identifies a fundamental speed limit imposed by noise.

Findings

Noise sets a fundamental limit to computing speed.

An optimal idle time interval minimizes error probability.

The model provides insights into noise-related speed constraints.

Abstract

In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold voltages. In this paper we discuss the role of noise in a two state model that mimic the dynamics of standard logic gates and show that the presence of the noise sets a fundamental limit to the computing speed. An optimal idle time interval that minimizes the error probability, is derived.