Pipelined Feed-Forward Cyclic Redundancy Check (CRC) Calculation

TL;DR

This paper introduces a pipelined, feed-forward architecture for CRC calculation that enhances scalability, flexibility, and efficiency, enabling CRC over packet tails and partial data updates.

Contribution

It presents a novel pipelined CRC computation method that supports independent scaling, tail processing, and partial data updates, improving over traditional approaches.

Findings

Supports CRC calculation over packet tails.

Allows CRC updates with partial data modifications.

Enables independent scaling of frequency and throughput.

Abstract

This paper discusses a method for pipelining the calculation of CRC's, such as ITU/CCITT CRC32, into a mostly feed-forward architecture. This method allows several benefits such as independent scaling of circuit frequency and data throughput. Additionally it allows calculation over packet tails (packet length not a multiple of CRC input width). Finally it offers the ability to update a CRC where a subset of data in the packet has changed.