Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

TL;DR

This paper introduces low power, high throughput BCD adders for IEEE 754r, utilizing novel two-transistor logic gates with minimal area and power consumption, suitable for floating point decimal computations.

Contribution

It presents novel two-transistor AND and OR gates without power supply or ground, and designs optimized BCD adders for IEEE 754r with reduced area and power.

Findings

Proposed AND gate is powerless; OR gate is groundless.

Designed carry skip and carry look-ahead BCD adders with improved efficiency.

Achieved reduced area and power consumption in BCD adder circuits.

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND and OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Groundless OR. Secondly for IEEE 754r format, two novel BCD adders called carry skip and carry look-ahead BCD adders are also proposed in this paper. In order to design the carry look-ahead BCD adder, a novel 4 bit carry look-ahead adder called NCLA is proposed which forms the basic building block of the proposed carry look-ahead BCD adder. Finally, the proposed two transistors AND and OR gates are used to provide the optimized small area low power high throughput circuitries of the proposed BCD adders.