VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics

TL;DR

This paper presents a hardware implementation of RSA encryption/decryption using Ancient Indian Vedic Mathematics algorithms, enhancing efficiency through modified multiplication and division architectures on FPGA.

Contribution

It introduces a novel FPGA-based RSA system utilizing Vedic algorithms for multiplication and division, improving performance over conventional methods.

Findings

Enhanced efficiency in RSA circuitry using Vedic division and multiplication.

Reduced area and increased speed compared to traditional architectures.

Successful implementation in Verilog HDL on Xilinx Spartan FPGA.

Abstract

This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures