Synth\`{e}se Comportementale Sous Contraintes de Communication et de Placement M\'{e}moire pour les composants du TDSI

TL;DR

This paper introduces a methodology and tool for high-level synthesis of DSP applications that optimizes performance and complexity under communication and memory constraints, demonstrated on an FFT case study.

Contribution

It presents a formal model-based approach and a tool, GAUT, enabling trade-offs in DSP design considering I/O timing and memory constraints.

Findings

Effective synthesis of FFT algorithm under constraints

Trade-off analysis between performance and complexity

Demonstrated feasibility on a real case study

Abstract

The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, our tool GAUT helps the designer in finding a reasonable trade-off between the circuit's performance and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.