A Memory Aware High Level Synthesis Too

TL;DR

This paper presents a novel memory-aware high-level synthesis approach that incorporates memory architecture constraints into the synthesis process, enabling optimized tradeoffs in time, power, and area for data-intensive applications.

Contribution

It formalizes memory mapping constraints as a Memory Constraint Graph and integrates them into HLS using the GAUT tool, improving synthesis quality.

Findings

Enables exploration of diverse memory configurations

Achieves better tradeoffs between time, power, and area

Incorporates memory constraints into scheduling process

Abstract

We introduce a new approach to take into account the memory architecture and the memory mapping in High- Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.