High-level synthesis under I/O Timing and Memory constraints

TL;DR

This paper introduces a methodology and tool for high-level synthesis of DSP algorithms that optimizes I/O timing and memory access constraints, demonstrated through an FFT case study.

Contribution

It presents a formal model-based approach and a generic architecture for high-level synthesis considering I/O and memory constraints, which is novel.

Findings

Effective trade-off between I/O timing and memory access achieved.

Tool successfully applied to FFT algorithm case study.

Demonstrates improved synthesis results under constraints.

Abstract

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.