Novel Reversible Multiplier Architecture Using Reversible TSG Gate
Himanshu Thapliyal, M.B Srinivas

TL;DR
This paper introduces a novel reversible multiplier architecture based on the TSG gate, enabling efficient, low-power computations suitable for quantum and nanotechnology applications.
Contribution
It presents the first reversible multiplier design using the TSG gate, optimizing gate count and garbage outputs compared to existing reversible multipliers.
Findings
Proposed 4x4 reversible multiplier architecture.
Reduced number of reversible gates and garbage outputs.
Demonstrated improved efficiency over existing reversible multipliers.
Abstract
In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. Recently a 4 * 4 reversible gate called TSG is proposed. The most significant aspect of the proposed gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. This paper proposes a NXN reversible multiplier using TSG gate. It is based on two concepts. The partial products can be generated in parallel with a delay of d using Fredkin gates and thereafter the addition can be reduced to log2N steps by using reversible parallel adder designed from TSG gates. Similar multiplier architecture in conventional arithmetic (using conventional logic) has been reported in…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum-Dot Cellular Automata · Parallel Computing and Optimization Techniques
