A Turbo Coding System for High Speed Communications

TL;DR

This paper introduces a novel turbo coding scheme with a special interleaver and multi-round early termination, enabling high-speed parallel processing, improved performance, and flexible decoder architectures for advanced communication systems.

Contribution

It proposes a new turbo coding scheme with an innovative interleaver and decoding strategy, allowing for inter-block collaboration and reduced decoding delay in high-speed communications.

Findings

Enhanced decoding performance with early termination and inter-block collaboration.

Reduced average decoding delay and increased throughput.

Flexible decoder architectures adaptable to various performance requirements.

Abstract

Conventional turbo codes (CTCs) usually employ a block-oriented interleaving so that each block is separately encoded and decoded. As interleaving and de-interleaving are performed within a block, the message-passing process associated with an iterative decoder is limited to proceed within the corresponding range. This paper presents a new turbo coding scheme that uses a special interleaver structure and a multiple-round early termination test involving both sign check and a CRC code. The new interleaver structure is naturally suited for high speed parallel processing and the resulting coding system offers new design options and tradeoffs that are not available to CTCs. In particular, it becomes possible for the decoder to employ an efficient inter-block collaborative decoding algorithm, passing the information obtained from termination test proved blocks to other unproved blocks. It also becomes important to have a proper decoding schedule. The combined effect is improved performance and reduction in the average decoding delay (whence the required computing power). A memory (storage) management mechanism is included as a critical part of the decoder so as to provide additional design tradeoff between performance and memory size. It is shown that the latter has a modular-like effect in that additional memory units render enhanced performance due not only to less forced early terminations but to possible increases of the interleaving depth. Depending on the decoding schedule, the degree of parallelism and other decoding resources available, the proposed scheme admits a variety of decoder architectures that meet a large range of throughput and performance demands.