A Machine-Independent port of the MPD language run time system to NetBSD

TL;DR

This paper discusses a portable implementation of the MPD language runtime system on NetBSD, leveraging POSIX threads to support SMP and multiple CPU architectures, with performance comparisons to traditional implementations.

Contribution

It introduces a machine-independent port of the MPD runtime system to NetBSD, enabling multi-architecture and SMP support using POSIX threads.

Findings

Supports 13 target CPUs with SMP on NetBSD.

Uses POSIX threads for portability and performance.

Provides performance comparisons with traditional implementations.

Abstract

SR (synchronizing resources) is a PASCAL - style language enhanced with constructs for concurrent programming developed at the University of Arizona in the late 1980s. MPD (presented in Gregory Andrews' book about Foundations of Multithreaded, Parallel, and Distributed Programming) is its successor, providing the same language primitives with a different, more C-style, syntax. The run-time system (in theory, identical, but not designed for sharing) of those languages provides the illusion of a multiprocessor machine on a single Unix-like system or a (local area) network of Unix-like machines. Chair V of the Computer Science Department of the University of Bonn is operating a laboratory for a practical course in parallel programming consisting of computing nodes running NetBSD/arm, normally used via PVM, MPI etc. We are considering to offer SR and MPD for this, too. As the original language distributions were only targeted at a few commercial Unix systems, some porting effort is needed. However, some of the porting effort of our earlier SR port should be reusable. The integrated POSIX threads support of NetBSD-2.0 and later allows us to use library primitives provided for NetBSD's phtread system to implement the primitives needed by the SR run-time system, thus implementing 13 target CPUs at once and automatically making use of SMP on VAX, Alpha, PowerPC, Sparc, 32-bit Intel and 64 bit AMD CPUs. We'll present some methods used for the impementation and compare some performance values to the traditional implementation.