A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices

TL;DR

This paper presents a practical circuit routing approach for dynamic NoCs on reconfigurable devices, offering a low-overhead, high-performance solution for communication management in FPGA-based systems.

Contribution

It introduces a novel 1D routing algorithm for dynamic NoCs and extends it to 2D, demonstrating efficiency and practicality for FPGA reconfigurable devices.

Findings

Low area overhead achieved

High routing performance demonstrated

Effective extension from 1D to 2D networks

Abstract

Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial reconfigurability is a new challenging problem. A Network-on-Chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.