Tree Parity Machine Rekeying Architectures

TL;DR

This paper presents a low-cost, fast, and flexible symmetric key exchange method using Tree Parity Machine synchronization, suitable for embedded systems with limited bandwidth, demonstrated through ASIC implementation.

Contribution

It introduces a novel rekeying architecture based on Tree Parity Machines, enabling quick key generation and adaptable security levels for embedded hardware.

Findings

Key exchange within a few milliseconds

ASIC implementation in 0.18-micrometer CMOS

Flexible security levels and short key lifetimes

Abstract

The necessity to secure the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e. small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronisation of Tree Parity Machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration we evaluate characteristics of a standard-cell ASIC design realisation as IP-core in 0.18-micrometer CMOS-technology.