Compact Floor-Planning via Orderly Spanning Trees

TL;DR

This paper introduces a simple, efficient algorithm for floor-planning in VLSI design based on orderly spanning trees, producing compact layouts with fewer module types and optimal area bounds.

Contribution

It presents a novel O(n)-time algorithm for floor-planning using orderly spanning trees, improving simplicity and area efficiency over previous methods.

Findings

Algorithm runs in linear time (O(n)).

Produces floor-plans with fewer module types.

Achieves near-optimal rectangular area (n-1) x (2n+1)/3).

Abstract

Floor-planning is a fundamental step in VLSI chip design. Based upon the concept of orderly spanning trees, we present a simple O(n)-time algorithm to construct a floor-plan for any n-node plane triangulation. In comparison with previous floor-planning algorithms in the literature, our solution is not only simpler in the algorithm itself, but also produces floor-plans which require fewer module types. An equally important aspect of our new algorithm lies in its ability to fit the floor-plan area in a rectangle of size (n-1)x(2n+1)/3. Lower bounds on the worst-case area for floor-planning any plane triangulation are also provided in the paper.