Chip-level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films
George Yong Liu (1), Ray F. Zhang (1), Kelvin Hsu (1), Lawrence, Camilletti (2) ((1) CMP Technology, Inc., (2) Conexant Systems Inc.)
TL;DR
This paper presents a chip-level CMP modeling approach for HDP and conformal CVD films, along with a smart dummy filling algorithm that improves pattern-density uniformity and CMP planarity.
Contribution
It introduces a novel chip-level CMP model and a smart dummy filling algorithm that enhances uniformity and planarity in CMP processes.
Findings
Model predictions agree well with experimental results.
The smart dummy algorithm improves pattern-density uniformity.
Enhanced CMP planarity achieved with the new dummy filling method.
Abstract
Chip-level CMP modeling is investigated to obtain the post-CMP film profile thickness across a die from its design layout file and a few film deposition and CMP parameters. The work covers both HDP and conformal CVD film. The experimental CMP results agree well with the modeled results. Different algorithms for filling of dummy structure are compared. A smart algorithm for dummy filling is presented, which achieves maximal pattern-density uniformity and CMP planarity.
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Taxonomy
Topics3D IC and TSV technologies · Semiconductor materials and devices · Copper Interconnects and Reliability