Characterization of All-Chromium Tunnel Junctions and Single Electron Tunneling Devices Fabricated by Direct-Writing Multilayer Technique

TL;DR

This paper presents the fabrication and analysis of Cr/CrO_x/Cr tunnel junctions and SET transistors created via a direct-writing multilayer technique, highlighting their electrical properties and noise performance.

Contribution

It introduces a novel direct-writing multilayer fabrication method for all-chromium tunnel junctions and SET devices, with detailed characterization of their electrical and noise properties.

Findings

Effective barrier height and thickness were determined for single junctions.

Achieved minimal junction area of 17 x 60 nm^2 for SET transistors.

Discussed electrical performance and noise behavior of the devices.

Abstract

We report about the fabrication and analysis of the properties of Cr/CrO_x/Cr tunnel junctions and SET transistors, prepared by different variants of direct-writing multilayer technique. In all cases, the CrO_x tunnel barriers were formed in air under ambient conditions. From the experiments on single junctions, values for the effective barrier height and thickness were derived. For the Cr/CrO_x/Cr SET transistors we achieved minimal junction areas of 17 x 60 nm^2 using a scanning transmission electron microscope for the e-beam exposure on Si_3N_4 membrane substrate. We discuss the electrical performance of the transistor samples as well as their noise behavior.