Nanoscale Field-Effect Transistors: An Ultimate Size Analysis

TL;DR

This paper presents an analytical model to analyze the size limitations of nanoscale dual-gate MOSFETs, revealing critical length scales where device performance deteriorates for logic and memory uses.

Contribution

It introduces a simple, solvable model for ballistic 2D electron dynamics in 10-nm-scale MOSFETs, providing insights into ultimate size limits for device functionality.

Findings

Voltage gain drops sharply at ~10 nm channel length.

Conductance modulation remains adequate for memory until ~4 nm.

Model predicts size thresholds for logic and memory applications.

Abstract

We have used a simple, analytically solvable model to analyze the characteristic s of dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with 10-nm-scale channel length L. The model assumes ballistic dynamics of 2D electrons in an undoped channel between highly doped source and drain. When applied to silicon n-MOSFETs, calculations show that the voltage gain (necessary for logic applications) drops sharply at L ~ 10 nm, while the conductance modulation remains sufficient for memory applications until L ~ 4 nm.