Gate Capacitance Coupling of Singled-walled Carbon Nanotube Thin-film Transistors

TL;DR

This paper analyzes the electrostatic gate capacitance in single-walled carbon nanotube thin-film transistors using analytical and finite-element models, validated by experiments, to inform device development.

Contribution

It provides a comprehensive analysis of gate capacitance coupling in SWNT TFTs considering quantum and classical limits, including experimental validation.

Findings

Capacitance depends on dielectric thickness and tube spacing.

Quantum and classical models show consistent trends.

Experimental results support the analytical and finite-element models.

Abstract

The electrostatic coupling between singled-walled carbon nanotube (SWNT) networks/arrays and planar gate electrodes in thin-film transistors (TFTs) is analyzed both in the quantum limit with an analytical model and in the classical limit with finite-element modeling. The computed capacitance depends on both the thickness of the gate dielectric and the average spacing between the tubes, with some dependence on the distribution of these spacings. Experiments on transistors that use sub-monolayer, random networks of SWNTs verify certain aspects of these calculations. The results are important for the development of networks or arrays of nanotubes as active layers in TFTs and other electronic devices.