Performance Analysis of a Ge/Si Core/Shell Nanowire Field Effect Transistor

TL;DR

This paper evaluates the performance of Ge/Si core/shell nanowire transistors using a semiclassical ballistic model and tight-binding electronic structure calculations, comparing experimental data with simulations to understand transport limits.

Contribution

It introduces a combined modeling approach to analyze nanowire transistor performance and compares experimental results with theoretical ballistic limits.

Findings

Experimental device operates at 60-85% of ballistic limit.

14-18 modes are occupied at room temperature.

True 1D transport requires nanowire diameter less than 5 nm.

Abstract

We analyze the performance of a recently reported Ge/Si core/shell nanowire transistor using a semiclassical, ballistic transport model and an sp3s*d5 tight-binding treatment of the electronic structure. Comparison of the measured performance of the device with the effects of series resistance removed to the simulated result assuming ballistic transport shows that the experimental device operates between 60 to 85% of the ballistic limit. For this ~15 nm diameter Ge nanowire, we also find that 14-18 modes are occupied at room temperature under ON-current conditions with ION/IOFF=100. To observe true one dimensional transport in a <110> Ge nanowire transistor, the nanowire diameter would have to be much less than about 5 nm. The methodology described here should prove useful for analyzing and comparing on common basis nanowire transistors of various materials and structures.