Comparison of near-interface traps in Al$_2$O$_3$/4H-SiC and Al$_2$O$_3$/SiO$_2$/4H-SiC structures

TL;DR

This study compares the interface trap densities in Al2O3/4H-SiC structures with and without an SiO2 interlayer, revealing differences in trap distributions that impact the potential for high-performance SiC-based MOSFETs.

Contribution

It provides a detailed analysis of near-interface traps in Al2O3/4H-SiC structures with different interfacial layers, highlighting their impact on device performance.

Findings

Al2O3/SiO2/4H-SiC has a high trap density at 0.3 eV below Ec.

Al2O3/4H-SiC exhibits a nearly trap-free region near Ec.

Trap densities vary between 0.4 to 0.6 eV below Ec.

Abstract

Aluminum oxide (Al2O3) has been grown by atomic layer deposition on n-type 4H-SiC with and without a thin silicon dioxide (SiO2) intermediate layer. By means of Capacitance Voltage and Thermal Dielectric Relaxation Current measurements, the interface properties have been investigated. Whereas for the samples with an interfacial SiO2 layer the highest near-interface trap density is found at 0.3 eV below the conduction band edge, Ec, the samples with only the Al2O3 dielectric exhibit a nearly trap free region close to Ec. For the Al2O3/SiC interface, the highest trap density appears between 0.4 to 0.6 eV below Ec. The results indicate the possibility for SiC-based MOSFETs with Al2O3 as the gate dielectric layer in future high performance devices.