Silicon Nanowires, Catalytic Growth and Electrical Characterization

TL;DR

This paper reports on the controlled growth of undoped silicon nanowires via catalytic chemical vapor deposition, their electrical characterization, and the fabrication of planar FETs demonstrating high on/off ratios and significant on-current.

Contribution

It introduces optimized growth techniques for undoped Si nanowires and demonstrates their effective use in high-performance FET devices with various silicide contacts.

Findings

Nanowire diameters controlled by catalyst thickness and plasma treatment.

FETs with 20 nm Si-NWs show high on/off ratios of 10^7.

Undoped Si-NWs exhibit higher conductance than previously reported.

Abstract

Nominally undoped silicon nanowires (NW) were grown by catalytic chemical vapor deposition. The growth process was optimized to control the NWs diameters by using different Au catalyst thicknesses on amorphous SiO2, Si3N4, or crystalline-Si substrates. For SiO2 substrates an Ar plasma treatment was used to homogenize the catalyst coalescence, and thus the NWs diameter. Furthermore, planar field effect transistors (FETs) were fabricated by implementing 10 to 30 nm thin nominally undoped Si-NWs as the active region. Various silicides were investigated as Schottky-barrier source and drain contacts for the active region. For CoSi, NiSi and PdSi contacts, the FETs transfer characteristics showed p-type behavior. A FET consisting of a single Si-NW with 20 nanometers diameter and 2.5 micrometer gate-length delivers as much as 0.15 microA on-current at 1 volt bias voltage and has an on/off current ratio of 10^7. This is in contrast to recent reports of low conductance in undoped Si.