Ianus: an Adpative FPGA Computer
Ianus Collaboration: F. Belletti, I. Campos, A. Cruz, L. A. Fernandez,, S. Jimenez, A. Maiorano, F. Mantovani, E. Marinari, V. Martin-Mayor, D., Navarro, A. Munoz-Sudupe, S. Perez Gaviro, G. Poli, J. J. Ruiz-Lorenzo, F., Schifano, D. Sciretti, A. Tarancon, P. Tellez

TL;DR
Ianus is a new FPGA-based machine designed for high performance and reprogrammability, aiming to outperform traditional computers on computationally demanding tasks with a flexible software platform.
Contribution
Introduction of Ianus, a reprogrammable FPGA-based machine optimized for performance, with plans for a user-friendly software platform to broaden its application scope.
Findings
Designed hardware integrates FPGA devices for high performance.
Plans for software platform to simplify programming.
Discussion on performance advantages over traditional computers.
Abstract
Dedicated machines designed for specific computational algorithms can outperform conventional computers by several orders of magnitude. In this note we describe {\it Ianus}, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability. Our goal is to build a machine that can fully exploit the performance potential of new generation FPGA devices. We also plan a software platform which simplifies its programming, in order to extend its intended range of application to a wide class of interesting and computationally demanding problems. The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their performance increase, as predicted by Moore's law. We discuss this point in detail.
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Distributed and Parallel Computing Systems · Embedded Systems Design Techniques
