Reversible and irreversible trapping at room temperature in poly(thiophene) thin-film transistors

TL;DR

This study investigates bias stress effects in poly(thiophene) thin-film transistors at room temperature, identifying reversible and irreversible charge trapping mechanisms and their kinetics, with implications for device lifetime estimation.

Contribution

It provides a detailed analysis of bias stress components in poly(thiophene) TFTs, highlighting the reversible and irreversible trapping processes and their kinetics at room temperature.

Findings

Bias stress has reversible and irreversible components.

Irreversible trapping follows power-law kinetics with exponent ~0.37.

Fast bias stress component is reversed at low duty-cycle.

Abstract

We measured the bias stress characteristics of poly(thiophene) semi-crystalline thin-film transistors (TFTs) as a function stress times, gate voltages and duty-cycles. At room temperature, the bias stress has two components: a fast reversible component and a slow irreversible component. We hypothesize that the irreversible component is due to charge trapping in the disordered areas of the semiconductor film. At low duty-cycle (<2%), the fast bias stress component is reversed during the off-part of the cycle therefore the observed VT shift in only caused by irreversible trapping. Irreversible trapping follows power-law kinetics with a time exponent approximately equal to 0.37. We use these findings to estimate the lifetime of TFTs used as switches in display backplanes.