Electrostatic Engineering of Nanotube Transistors for Improved Performance

TL;DR

This paper demonstrates that asymmetric electrostatic design significantly enhances carbon nanotube transistors by reducing off currents and enabling versatile p- or n-type operation, especially in Schottky-barrier CNFETs.

Contribution

It introduces an asymmetric electrostatic engineering approach that improves CNFET performance and allows dual-type operation with a single device design.

Findings

Asymmetric design reduces off currents in CNFETs.

Performance improvement is most significant in Schottky-barrier CNFETs.

Single device can function as both p- and n-type by changing drain voltage sign.

Abstract

With decreasing device dimensions, the performance of carbon nanotube field-effect transistors (CNFETs) is limited by high Off currents except at low drain voltages. We show that an asymmetric design improves the performance, reducing Off currents and extending the usable range of drain voltage. The improvement is most dramatic for ambipolar Schottky-barrier CNFETs. Moreover, this approach allows a single device to exhibit equally good performance as an n- or p-type transistor, by changing only the sign of the drain voltage. Even for CNFETs having ohmic contacts, an asymmetric design can greatly improve the performance for small-bandgap nanotubes.