Accelerating hybrid XOR–CNF Boolean satisfiability problems natively with in-memory computing
Haesol Im, Fabian Böhm, Giacomo Pedretti, Noriyuki Kushida, Moslem Noori, Elisabetta Valiante, Xiangyi Zhang, Chan-Woo Yang, Tinish Bhattacharya, Xia Sheng, Jim Ignowski, Arne Heittmann, John Paul Strachan, Masoud Mohseni, Raymond Beausoleil, Thomas Van Vaerenbergh

TL;DR
This paper introduces a hardware accelerator for solving complex Boolean satisfiability problems using in-memory computing, achieving significant speed and energy efficiency improvements.
Contribution
A novel hardware architecture that natively solves hybrid XOR–CNF SAT problems using in-memory computing with memristor crossbar arrays.
Findings
The accelerator improves computation speed, energy efficiency, and chip area utilization by ~10× for cryptographic problems.
It achieves ~10× speedup and ~1000× energy efficiency gain over state-of-the-art SAT solvers on CPUs.
Abstract
The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by representing them with a combination of exclusive OR (XOR) and conjunctive normal form (CNF) clauses. We propose a hardware accelerator architecture that natively embeds and solves such hybrid XOR–CNF problems using in-memory computing hardware. To achieve this, we introduce an algorithm and demonstrate, both experimentally and through simulations, how it can be efficiently implemented with memristor crossbar arrays. Compared to the conventional approaches that translate XOR–CNF problems to pure CNF problems, our simulations show that the accelerator improves computation speed, energy efficiency, and chip area utilization of in-memory…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · DNA and Biological Computing · Advanced Memory and Neural Computing
